LMH1983: Jitter performance for 12G SDI

Hirokazu Takahashi

Expert 8420 points

Part Number: LMH1983

Hello Support team,

Can LMH1983 support 12G-SDI clock requirements?

Is it necessary to put any jitter cleaner to 12G SDI driver and equalizer?

If it is true, please let me know the proper jitter cleaners.

Best Regards,

Hirokazu Takahashi

over 3 years ago

0 Noel Fung over 3 years ago

TI__Guru** 108610 points

Hi Takahashi-san,

LMH1983 is a jitter cleaner + clock generator, I don't think cable driver and equalizer need a clock signal. The output clocks from LMH1983 are usually used as the reference clocks of a FPGA (serializer). As such, the requirement to the clocks will be came from FPGA / serializer. Do you have the requirement from the customer?

0 Hirokazu Takahashi over 3 years ago in reply to Noel Fung

TI__Expert 8420 points

Hello Noel-san

Thanks for your support.

You are right. LMH1983 is connected to FPGA.

So, does 12G SDI performance depend on the PLL integrated in FPGA?

Is it necessary to put any clock cleaner in order to improve phase noise, jitter and etc.?

Best Regards,

Hirokazu Takahashi

0 Noel Fung over 3 years ago in reply to Hirokazu Takahashi

TI__Guru** 108610 points

Hi Takahashi-san,

Yes, the PLL inside FPGA will affect the performance, so the FPGA should have a phase noise requirement for the input clock in order to ensure that the overall jitter performance is met. Whether an external clock generator or GenLock is necessary depends on the FPGA performance and the system architecture, the customer should be able to tell.

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LMH1983: Jitter performance for 12G SDI