Hi team,
Customer plans to use LMK05028 as Hard pin mode by pulling high at HW_SW_CTRL pin.
1. After start-up, does customer need to write all register map generated by TICS Pro, right?
2. To change the output frequency, what is the recommended procedure?
3. When changing the output frequency, is it okay that change only the corresponding registers? Or all register map should be overwrote?
Best regards,
Hideki
Hideki-san,
1. After start-up, the customer either loads a saved configuration or uses the wizard with steps 1-6.
2. Ideally you use the "wizard". If the configuration of DPLL/APLLs is already done with the wizard then you can also change the output divider manually. This can only change the output to related frequencies to the VCO. You may want to assert a SYNC again to have the outputs aligned again.
3. see above.
regards,
Julian
Hideki-san,
an easy way to monitor the register changes is to look at the status bar. All register writes are logged in there.
There is no control when you change the output divider. If a new divider value is written in the register the frequency will change immediately. Disabling the output first, then updating the divider and followed by enabling the output again is a good approach.
regards,
Julian
Hello Hideki-san,
At this point, we don't have a simple way to separate the read only from the write registers to generate a minimum write sequence simply, however the register documentation contains this information for each register. For example:
On the "Main: Start Page" we have added buttons to generate register sets for DPLLx, and DPLLx + outputs.
Perhaps you could meet your requirements for knowing which registers to program by using DPLLx + outputs and examining the resulting text file output. It has comments to see what area is changing. Note it also includes masks so you don't impact other fields related to other items.
Your sequence would work, to make a change and then do a reset, however... it is my understanding it is not required to do a full RESET_SW which changing this values, you could reset only APLL1/DPLL1 for example:
# APLL1/DPLL1 Reset
R677 0x02a501 & 0x000001
R677 0x02a500 & 0x000001
You can also use the first end ending lines to power down outputs while changing... Note this is sensitive to the current configuration depending on how many outputs from from DPLLx (DPLL1 in this example).
# First power down the outputs changing
R51 0x00333f & 0x00003f
# Last power up the outputs
R51 0x00330f & 0x00003f
73,
Timothy
