LMK04832: ClkIn0 Adjust Input Frequency Range

Grant Skeels

Part Number: LMK04832

Hello Team,

Utilizing the configuration attached, I am seeing the PLL1 loose DLD after the input frequency drops from 10MHz to 9.9995MHz. Based on my system design, I am expecting some variation in the input clock feeding the PLL.

Is there a setting in TICS Pro that would allow this?

Thanks again for your help!!
Default.tcs

over 4 years ago

0 Ajeet Pal over 4 years ago

TI__Genius 12590 points

Hi,

It seems there is an similar / repeat thread already present.

(+) LMK04832: PLL Looses Lock with a 10 MHz signal - Clock & timing forum - Clock & timing - TI E2E support forums

Hope, it helps you.

Thanks!

Regards,

Ajeet Pal

0 Grant Skeels over 4 years ago in reply to Ajeet Pal

Prodigy 45 points

Hi Ajeet,

Thanks for the reply, I did see this post but was wondering if there was a solution that could avoid hardware modifications.

I am using the LMK04832 in dual loop mode (holdover disabled), so when ClkIn0 drops by 500Hz I loose DLD on PPL1 but the DAC remains locked keeping PLL2 in DLD.

Is there a configuration or register in the LMK04832 that I can modify to increase the input BW of PLL1?

Thanks again!

0 Ajeet Pal over 4 years ago in reply to Grant Skeels

TI__Genius 12590 points

Hi Grant,

Instead of changing the loop filter components, I would suggest to try with increasing the Kpd, which would turn to increase the input BW of PLL1. It would try to track the change in input reference signal.

Thanks!

Regards,

Ajeet Pal

0 Grant Skeels over 4 years ago in reply to Ajeet Pal

Prodigy 45 points

Hi Ajeet,

Thanks for the suggestion, I did try increasing the Kpd to 650uA without any luck. I worry ramping it up too high will introduce in-stability into the system.

I also monitored the DAC status during the loss of DLD, it appears that the DAC stops updating after DLD is lost. Given I have holdover disabled, is this expected? I would have figured the DAC would continue to update as it attempts to re-acquire DLD?

Thanks again,

Grant

+1 Ajeet Pal over 4 years ago in reply to Grant Skeels

TI__Genius 12590 points

Hi Grant,

Have you tried with holdover enable option also? If there is still loss of DLD, I believe you need to go with higher PLL1 loop BW, which can tolerate the variation in input frequency.

Thanks!

Regards,

Ajeet Pal

0 Grant Skeels over 4 years ago in reply to Ajeet Pal

Prodigy 45 points

Hi Ajeet,

I have tried with the holdover enabled option. In this case, the unit will enter holdover and never recover the from the PLL1 DLD loss.

After modifying the hardware's loop filer, this issue has gone away.

Thanks for all your help!