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CDCLVD1204 minimum freq.

Michael Parkanski
Prodigy 375 points
Other Parts Discussed in Thread: CDCLVD1204

Hi

 

Customer is designing a system that requires clock buffer with 3 LVDS clock outputs/ and ultra low jitter

Clock freq. options: 19.2MHz, 26MHz, 38.4MHz and 52MHz (only one freq shall be active)

Preferred voltage 2.5V

and inspecting TI/ CDCLVD1204 device

 

1.       Can this device supports this (low) freq. ?

2.       In this low freq. can the device support min input voltage of 0.25V ?

 

Thanks,

Michael

  • 0
    TI__Expert 5725 points

    Hi Michael,

    For an LVDS input signal (as can be seen on page 4 of the datasheet) this buffer is able to handle up to 800MHz, therefore 19.2MHz is no problem. The only careabout is that a minimum slew rate of 0.75V/ns needs to be met.

     

    The minimum differential voltage VINDIFFpp that can be accepted is 0.3Vpeaktopeak. When you are referring to min input voltage of 0.25V, are you referring to the amplitude of one of the differential inputs?

     

  • 0 in reply to mapefer3
    TI__Prodigy 375 points

    Thanks for your answers they are very helpful for the customer,


    For your info, regarding min. VIN_DIFFpp: 0.3Vp-p
    Attached the pages of the XO outputs (from DS)
    As you can see the min. amplitude is 250mV (on 100Ω load), I already asked the XO manufacturer
    If I can put a 120Ω resistor instead of 100Ω to reach 0.3V VINDIFFpp

    Can you please answers further question

    1.      TI/ CDCLVD120 minimum slew rate of 0.75V/ns – This requirement is unclear to me
    In order to meet this requirement
    The XO rise/ fall times are max of 400pS, does it meet the required min slew rate
    TI/ CDCLVD120 outputs are much fasters (300pS)

    Thanks,

    images.zip
  • 0 in reply to Michael Parkanski
    TI__Expert 5725 points

    Your customer’s device is meeting the specifications for the CDCLVD1204.

     

    VIDdiffpp is INP0-INN0, and the slew rate is calculated based on that.

     

    In the definition of your product each of the individual signal has a minimum swing of 250mV, therefore the differential swing (positive clock-negative clock) would present a differential minimum swing of 500mVpp, and if the rise and fall time of each of them is 400psmax, that would imply that a slew rate comparable with our specification would be 500mVpp/0.4ns=1.25V/ns>0.75V/ns therefore it is within our specification.