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CDCM7005-SP: phase alignment and delay after reset

Kazuhiko Hirano
Genius 13888 points
Part Number: CDCM7005-SP

Hello,

My customer would like to use CDCM7005-SP as follows.

- VCXO_IN --> PDIV=/2 --> Y0A(LVPECL)
- VCXO_IN --> PDIV=/4 --> Y1A(LVPECL)
- VCXO_IN --> PDIV=/8 --> Y2A(LVPECL)
- VCXO_IN --> PDIV=/16 --> Y3A(LVPECL)

About this usage, they have some questions as follows.

Q1:
Y0A, Y1A, Y2A and Y3A rising edge phases are aligned once 16 VCXO_IN cycles as follows?
Or a reset is required to align them as follows?

Q2:
In Figure 11 of the datasheet, how much is the maximum tpd(LH), maximum tpd(HL), minimum tpd(LH) and minimum tpd(HL) for LVPECL output respectively?

Q3:
How much is the delay from deassertion of reset_ to YnA output first rising edge?

Best regards,

K.Hirano

  • 0
    TI__Genius 13888 points

    CTS team,

    My customer is awaiting your team feedbacks.
    Could someone in CTS team respond, please?

    Best regards,

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Mastermind 31680 points

    Hirano-san,

    Q1: After programming the muxes to route the divided outputs, the P-counter should probably be reset by toggling RESET_ pin. I am not sure if this happens automatically by default when divider values are modified.

    Q2: We don't have any characterization data on minimum or maximum for these values. These parameters are also not tested during production, so we have no production data to help suggest limits. I have no good answer for this question.

    Q3: The RESET_ function is asynchronous with the VCXO, so there is no guaranteed delay from reset to YnA output first rising edge. I see around 90µs typical delay between reset edge toggle and clocks deasserting or asserting.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    TI__Genius 13888 points

    Derek,

    Thank you for your responses.

    Best regards,

    K.Hirano