Hello E2E,
I’m looking to use CDCDB800RSLR LP-HCSL 1:8 clock buffers to provide 100MHz PCIe reference clocks across a system. The datasheet for this component mentions that it expects an LP-HCSL input clock, but in our case we’re stuck with an LVDS input clock.
The clock input characteristics seem to suggest that LVDS might work, but there are no mentions of other clock standards / termination schemes outside of LP-HCSL.
Can you confirm whether or not LVDS input clocks are compatible with this component? If so, can you let us know if there are any additional termination recommendations outside of 85 ohms across the input? (we’re routing 85 ohms differential)
Thank you!
Russell
