CDCI6214: LVCMOS jitter, and output channels

wang shu

Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214

Hi,

1. I wish to use CDCI6214 to generate four 2MHz LVCMOS clocks. i suppose to make output2&3 to CMOSP and P+/N+ in TICS software, then the pin 13,14,17,18 will generate four 2MHz LVCMOS clock, am i right?

2. I use the CDCI6214 because i have one to generate LVPECL clock, so i wish to use same part. But there is no LVCMOS output jitter information in the datasheet. Do you know what RMS jitter from 12kHz to 20MHz for LVCMOS signal? I saw the CDCE6214 has some information show the max LVCMOS jitter is 1.5ps for Integer mode. The max jitter for my design is 1.5ps. but I don’t want to use CDCE6214 because it cannot replace the existing CDCI6214 to generate LVPECL signal.

3. If CDCI6214 cannot has LVCOMS low jitter than 1.5ps. what buffers could I use to generate 4 channel 2MHz LVCMOS with low jitter? And I also can use it to generate LVPECL clocks. Of cause, I wish the price is close the CDCI6214.

Regards,

Shu

over 3 years ago

0 vicente flores prado over 3 years ago

TI__Mastermind 29542 points

Hi Shu,

1. That is correct.

2. RMS jitter is typically provided for common output frequencies, given your output frequency of 2MHz, we do not have this formation. The 1.5ps listed for max LVCMOS RMS Jitter is assuming your output frequency is greater than 100MHz. Given your low 2Mhz output frequency, the RMS jitter should be lower than 1.5ps so this will not be an issue.

Regards,

Vicente

0 vicente flores prado over 3 years ago in reply to vicente flores prado

TI__Mastermind 29542 points

Hi Shu,
One more thing. Given you're outputting only 2MHz signals from an 80MHz input, you can actually bypass the PLL and just use the output dividers for better jitter performance.

Regards,

Vicente

0 wang shu over 3 years ago in reply to vicente flores prado

Intellectual 300 points

Hi Vicente.

1. the 1.5ps RMS jitter is from CDCE6214. Do you have the LVCOMS jitter feature for CDCI6214? i lony can see the jitter for LVDS and HCSL signal in the datasheet.

2. I need to synchronize the 2MHz to main 80MHz. So bypass the PLL cannot do that, right?

Regards,
Shu

+1 vicente flores prado over 3 years ago in reply to wang shu

TI__Mastermind 29542 points

Hi Shu,
1. We do not have that specification but your requirement will be met. Note how in the datasheet the those values are listed for common output frequencies.

2. If you require synchronization, then unfortunately no you cannot bypass PLL.

Regards,

Vicente

0 wang shu over 3 years ago in reply to vicente flores prado

Intellectual 300 points

HI Vicente,

Thank you very much. Now I am confident to use CDCI6214 in my design to generate 2MHz LVCOMS clock with 1.5ps lower jitter.

Regards,
Shu

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CDCI6214: LVCMOS jitter, and output channels