Hi Team
I was trying to verify my frequency plan by using the clock design tool, but didn't find the configuration model of LMK05028 installed.
https://www.ti.com/tool/CLOCKDESIGNTOOL
Is there a way to use this design tool for verifying the frequency plan of LMK05028?
If not, is there any other tool I can use & could you help checking whether the frequency plan/pin-out as below looks fine?
Setting①
・IN0_P/N:388.8MHz、AC-Coupled LVDS(★Connect to PLL1)
・IN1_P/N:388.8MHz、AC-Coupled LVDS(★Connect to PLL2)
・XO_P(N):48MHz、Single-Ended LVCMOS XO
・OUT7_P/N:155.52MHz、AC-Coupled LVDS(★Generated by PLL1 or the 48MHz XO)
・OUT5_P/N:155.52MHz、AC-Coupled CML (★Generated by PLL1 or the 48MHz XO)
・OUT2_P/N:155.52MHz、AC-Coupled CML (★Generated by PLL2 or the 48MHz XO)
・OUT0_P/N:155.52MHz、AC-Coupled LVDS(★Generated by PLL2 or the 48MHz XO)
Setting②
・IN0_P/N、IN1_P/N、XO_P(N) same as the setting①
・OUT7_P/N:155.52MHz、AC-Coupled LVDS(★Generated by PLL1 or the 48MHz XO)
・OUT5_P/N:155.52MHz、AC-Coupled CML (★Generated by PLL1 or the 48MHz XO)
・OUT2_P/N:156.25MHz、AC-Coupled CML (★Generated by PLL2 or the 48MHz XO)
・OUT0_P/N:156.25MHz、AC-Coupled LVDS(★Generated by PLL2 or the 48MHz XO)
Setting③
・IN0_P/N、IN1_P/N、XO_P(N) same as the setting①
・OUT7_P/N:161.13MHz、AC-Coupled LVDS(★Generated by PLL1 or the 48MHz XO)
・OUT5_P/N:161.13MHz、AC-Coupled CML (★Generated by PLL1 or the 48MHz XO)
・OUT2_P/N:156.25MHz、AC-Coupled CML (★Generated by PLL2 or the 48MHz XO)
・OUT0_P/N:156.25MHz、AC-Coupled LVDS(★Generated by PLL2 or the 48MHz XO)
Setting④
・IN0_P/N、IN1_P/N、XO_P(N) same as the setting①
・OUT7_P/N:161.13MHz、AC-Coupled LVDS(★Generated by PLL1 or the 48MHz XO)
・OUT5_P/N:161.13MHz、AC-Coupled CML (★Generated by PLL1 or the 48MHz XO)
・OUT2_P/N:644.531MHz、AC-Coupled CML (★Generated by PLL2 or the 48MHz XO)
・OUT0_P/N:644.531MHz、AC-Coupled LVDS(★Generated by PLL2 or the 48MHz XO)
Setting⑤
・IN0_P/N:388.8MHz、AC-Coupled LVDS(☆Connect to PLL2)
・IN1_P/N:388.8MHz、AC-Coupled LVDS(☆Connect to PLL1)
・XO_P(N):48MHz、Single-Ended LVCMOS XO
・OUT7_P/N:155.52MHz、AC-Coupled LVDS(☆Generated by PLL1 or the 48MHz XO)
・OUT5_P/N:155.52MHz、AC-Coupled CML (☆Generated by PLL1 or the 48MHz XO)
・OUT2_P/N:155.52MHz、AC-Coupled CML (☆Generated by PLL2 or the 48MHz XO)
・OUT0_P/N:155.52MHz、AC-Coupled LVDS(☆Generated by PLL2 or the 48MHz XO)