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CDCDB2000: CDCDB2000NPPR rising /falling time too fast

Lawrence He
Expert 2740 points
Part Number: CDCDB2000

Hi, Support Team

We have question about for CDCDB2000NPPR

Could we fine tune rising /falling time slowly by register?

Fail item:

TI CDCDB2000

3. CPU1_BCLK0 (SKU3): Diff rising/falling slew rates are out of spec.

7. 1U_Riser (SKU3): Diff rising/falling slew rates are out of spec.

8. 2U_Riser_Port0 (SKU3): Diff rising/falling slew rates are out of spec.

9. 2U_Riser_Port1 (SKU3): Diff rising/falling slew rates are out of spec.

10. M2 Riser_J1 (SKU3): Diff rising/falling slew rates are out of spec.

11. M2 Riser_J2 (SKU3): Diff rising/falling slew rates are out of spec.

12. LOM_100M (SKU3): Diff rising/falling slew rates are out of spec.

 

For example fail below

According to the Eagle Stream Platform EDS Rev 2.0, the maximum of slew rate is 4 V/ns.
so about the slew rate is can not meet the Intel EDS?

if any suggestion, Please advise me.

Thanks,

Best regards,

Lawrence

  • 0
    TI__Genius 11095 points

    Hi Lawrence,

    I am not aware of any register settings in the CDCDB2000 that can control the slew rate of the output clocks. A clock buffer is generally intended to copy the input clock without making changes. Does the input clock also have problems with being out of spec?

    I will check with my team tomorrow to see if there is anything else we can do.

    Thanks,

    Evan Su

  • 0 in reply to Evan Su
    TI__Genius 11095 points

    Hi Lawrence,

    We have previously been told by Intel that a higher slew rate than 4 V/s is OK and would not cause problems. However the customer may want to check their system with Intel to be sure. Let us know if there are other questions.

    Best,

    Evan Su