Hello E2E Experts,
Good day.
The Device Under Test (DUT) is an ASIC with a single-ended clock input. We are trying to minimize any clock phase jitter using the LMK05028.
1. Should we configure the OUT0 clock driver to be single-ended or come out differential and use a buffer to convert to single-ended?
2. Are there recommended power/grounding schemes that would help minimize any potential phase jitter?
From a layout perspective, there may be an inch between the LMK05028 and the DUT.
Regards,
CSC
