LMK04828: Distribution Mode - All DCLK Output Synched/Phase aligned

I'll revise my answer to be more clear:

• All the SDCLK outputs will be aligned regardless of SYNC behavior, provided they have the same local delay settings (digital and analog). They all share a common divider in your example, so if their local delays are the same, they should all share a common phase alignment.
• If you want all outputs to be aligned to the input, i.e. there is always an input edge for every output edge, this is guaranteed in distribution mode since as you say there's only dividers in the output path and they all derive from the input reference.
• If you want all outputs to be aligned to each other, i.e. every device clock divider shares the same input clock cycle for their rising edges, or every device clock shares a common phase offset to the SDCLKs, you need to SYNC (and it's not timing-critical). When you initially program the registers for the dividers, the dividers get reset, and the timing of the divider reset is effectively random, so all output clocks in your example will have effectively one of ten possible phases and there are no guarantees that any device clocks will share a phase until manually SYNCed.
  
  • You could program the SYNC_EN, SYNC_MODE, SYNC_DISx, SYSREF_MUX, and SYNC_POL fields before anything else after POR/RESET, to hold the entire output divider network in the reset state; then once all other programming is complete, clear SYNC_POL, set all SYNC_DISx, and switch SYSREF_MUX to continuous. Note that it implicitly requires CLKIN1 to be running after POR since the SYNC_MODE mux is retimed to the clock distribution path. 
  • If you somehow arrange to never provide CLKIN1 between when POR/RESET occurs until after all registers are programmed, and can guarantee that CLKIN1 is noise-free in the idle state, it is conceptually possible to skip providing a SYNC, program the dividers, and trigger all resets before ever providing a distribution clock; since divider reset occurs in a deterministic number of distribution clock cycles for all dividers, all dividers would be aligned to a repeatable phase the moment CLKIN1 signal is provided. I don't recommend attempting this, because the input buffer is internally AC-coupled with a few tens of mV of hysteresis, so it doesn't take much stray noise during the programming process to unintentionally trigger a distribution path clock cycle before all divider registers are written (particularly if the CLKIN1 source tri-states instead of staying low-impedance during the off-period).