Hello expert,
Do we have timing requirement between PD and VCC? I checked datasheet page 10 and there is #PD reqiurements but i didn't find the graph to specific point out the relation between VCC and #PD. Could you provide the graph or more clear timing requirement for PD and VCC? Thanks!
Best regards,
Ann Lien
Ann,
There is a requirement for the SPI_LE pin to be high before the transition of the /PD pin from L to H. See here:
The datasheet notes that the maximum rise time should be 4 ns - I believe that this is actually meant to be a minimum rise time:
This is only for loading the EEPROM into the registers - the registers can alternatively be programmed through the communication interface - see this thread: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/335316/cdce62002---would-it-be-a-problem-if-pd-pin-fixed-to-logic-high-or-floating?tisearch=e2e-sitesearch&keymatch=cdce62002%25252525252520pd#
Thanks,
Kadeem
