Hello there TI team,
I am hoping you can provide a schematic review for a my design for a client. I am providing a 36.864MHz oscillating clock into the LMK and then outputting it to two microcontrollers and one ADC (a Texas Instruments TLV320). Is it okay that I tie the 1G high so that it starts as soon as Vdd is stable? Then when I bring the oscillator up the buffer will then pass out the clock signal? Additionally, is it okay that I do my fanout signal impedance balancing by simply calculating the impedance of the trace to the sink IC and then add a resistor in series to bring the overall impedance up to 50ohms?
Thanks so much,
Peter