LMX2485E: LMX2485E Configuration

switch

Part Number: LMX2485E

Tool/software:

Hi ti team，

Could you please provide the configuration guide for LMX2485E? My client's new project is currently utilizing this component, but we are unaware of how to configure it. Thank you!

over 1 year ago

0 Noel Fung over 1 year ago

TI__Guru** 111720 points

Hi There,

Please use TICS Pro to configure the device, you can also export the register settings to a text file.

https://www.ti.com/tool/TICSPRO-SW

0 switch over 1 year ago in reply to Noel Fung

Genius 3880 points

Hi Noel,

1. I successfully output the data needed to configure the registers using TICS Pro. Currently, the OSC is 19.2Mhz, and I only need to configure the RF high frequency to 650Mhz, the Fpd to be close to 200kHz (bandwidth), and the IF intermediate frequency is not needed. Therefore, the data is as follows:

R0 0xCB0000

R1 0xB0FA03

R2 0x001385

R3 0xFF00A7

R4 0x20C549

R5 0x00000B

R6 0x3C000D

R7 0x00090F

2) To make the LMX2485E work, I pulled LE low, CE high, and ENOSC high. During configuration, the CLK period was approximately 37us. After writing 24 bits of data to the register, I would pull LE high and 17us later pull it low.

Then there are the following questions:

1. I verified that the data and clock signals on the logic analyzer were normal. However, when I looked at the frequency with a spectrum analyzer, it was unchanged, and no matter how long I waited, the LD was not pulled up using a multimeter. Could you please provide a reference for the effective timing of Data and Clock?

2. Can you provide the driver for the EVM?

0 Noel Fung over 1 year ago in reply to switch

TI__Guru** 111720 points

Hi switch,

According to your register setting, your configuration will be as follows, it does not match with your description.

you should change the configuration to below. Charge pump gain setting depends on your loop filter design.

Since you use IF PLL, you should set the MUX to IF lock detect output.

the final register value will look like below.

0 weldon pan over 1 year ago in reply to Noel Fung

Prodigy 40 points

Sorry mate, I was asking about using RF PLL to generate 650Mhz while Fpd is 400kHz. The register value is now

I am not sure my hardware is correct, can you check it for me as well. TA.

0 Noel Fung over 1 year ago in reply to weldon pan

TI__Guru** 111720 points

Hi Weldon,

You can use PLL Sim (www.ti.com/.../PLLATINUMSIM-SW) to design and simulate the loop filter.

0 weldon pan over 1 year ago in reply to Noel Fung

Prodigy 40 points

The design is follow as(Vbias is 1.65V):

However, once I power up the PLL and VCO, the CpoutRF will soon drop to 0V, so as the output of the loop filter. The output of the loop filter also rise to 13V after it stay 0V for few seconds.

My start up sequence is CLK, Data, CE, ENOSC set HI, LE set LOW, after around 5ms, I start to write register values. I set LE HI for 18us then set it LOW for each address.