LMX2571: LMX2571 Frequency out is floating XXhz range

Hi Kim,

Is the 100MHz clock clipped sine wave or CMOS?

I am not sure if it is related but Fden should not be zero.

After Vcc power up, program all the necessary registers in descending order, the last register is R0 (FCAL_EN must be =1). 

1. The ref clock is from CMOS crstal osillator.-> but I measure it with tektronix it is sine wave 1.9V to 1.21V

2. I changed Fden but same situation so now I just except the Fractal N divide option

3. I send SPI data started from R60 to R0 and FCAL_EN is being 1.

After R0 is sent MUX pin out high so it says locked

Hi Kim, 

Sungjin Kim said:

After R0 is sent MUX pin out high so it says locked

Are you saying after following Noels steps you were able to achieve lock & LD is high? That's what I understand. 

Regards, 

Vicente

No I mean I did it already before he said

I am first at PLL but I think the main asking what I doing is 

"How can I set F_out in 1Hz level stablility"

And the answer is maybe I think setting CPout's loop filter(2nd order shaped) components with suitable loop bandwidth

So now I am trying PLLatinum sim... But it is hard