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LMX2820: LMX2820

Deepa Pattar
Prodigy 20 points
Part Number: LMX2820

Tool/software:

Is it possible to use a 10 kHz loop bandwidth with feasible loop filter parameters? If so, what would be the approximate maximum lock time?

  • 0
    TI__Mastermind 29172 points

    Hi Deepa,

    Please use PLLatinumSim to estimate lock time and calculate optimal loop filter values.

    A good approximation for lock time is 4/LBW so 4/10kHz = 400us

    Typically loop bandwidth should be as wide as possible for fastest lock time. Narrow loop bandwidths are for jitter cleaning applications.

    Regards,

    Vicente

  • 0 in reply to vicente flores prado
    Prodigy 20 points

    Thank you for your reply. Yes, I am using PLLatinumSim to estimate loop filter parameters and lock time. It is providing feasible loop filter parameters for a 10 kHz loop bandwidth, and the lock time is 100 µs. However, according to the formula 4/LBW, 4/10 kHz = 400 µs. Could you please elaborate on what the factor of 4 indicates in this context?

  • 0 in reply to Deepa Pattar
    TI__Guru** 107780 points

    Hi Deepa,

    4/LBW is just an rough estimation, actual lock time also depends on frequency jump size, phase margin, settle tolerance, VCO calibration, etc.

    PLL Sim will take all of these parameters into account.

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Thank you for your valuable response regarding loop bandwidth and lock time calculation. I have a clarification question on one more topic. In PLLatinumSim, it is recommended that the loop filter capacitor (C3, for a 3rd order passive filter) close to the VCO should be at least 1.5nF. Are there similar constraints for C1 and C2 in the same filter?

  • 0 in reply to Deepa Pattar
    TI__Guru** 107780 points

    Hi Deepa,

    No, no such requirement to C1 and C2.

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Hi Noel,

    In PLLatinum Sim, the spur level for 8000.025 MHz is less than -70 dBc. However, when I tested it with a spectrum analyzer using the same loop filter parameters compare to default loop parameter (mentioned in eval board data sheet), the spurious levels were higher. For further clarification, I am attaching the SIM picture and a picture of the test results.

    PLL configuration parameters (instant calibration)

    Integer : 40

    Numerator : 1

    Denominator : 8000

    instantcal : 536871

    fig(1). PLLatinumSim result

    fig (2). test result (loop filter parameter with default value)

    fig(3). test result (loop filter parameter mentioned in PLLatinumSim)

  • 0 in reply to Deepa Pattar
    TI__Guru** 107780 points

    Hi Deepa,

    Given reference = fpd = 200MHz and VCO = 8000.025MHz, for sure there will be an IBS at 25kHz offset.

    If reducing the loop bandwidth cannot reduce this spurs, that means this spurs is mainly due to crosstalk. 

    As such, there is little we can do to further reduce the spurs. We can try using differential reference clock or use other non-integer multiple frequency.