LMK5C33216EVM: LMK5C33216EVM: Synchronisation with a external 10 MHz sinuswave

Hi Patrice,

Can you please clarify the XO input frequency? Is it 38.88 MHz from the on board TCXO?

Regards,

Jennifer

Hello Jennifer,

Yes it is 38.88 MHz TCXO (38.88-MHz, 3.3-V LVCMOS, low-jitter TCXO, snau260a.pdf, LMK5C33216EVM User's Guide).

Regards,

Patrice

Hello Jennifer,

Thank you for .tcs file. I have tried to test it with the LMK5C33216EVM but I did not succeed to lock.

From the registers, the ref_valid_status is well detected when I put the 10MHz in IN0 or IN1.

I never see LOPL, LOFL from DPL2 unchecked.

Maybe I sould release constraints, isn't it?

Do you have any way to debug it or advices.

Thank you,

Regards,

Patrice

Hi Patrice,

From your Status page screenshot, I see that DPLL3 is locked. In the configuration I sent you, I only enabled DPLL3 because only one synchronization domain is needed to lock to the IN=10MHz input. Therefore, you may ignore the DPLL2-3 status signals.

Can you connect INx and OUTx to a scope? If you can trigger the outputs to INx, then the DPLL is locked.

Regards,

Jennifer

Hello Jennifer,

I have triggered to the 40 MHz output but the INx is moving with lopl_DPLL3 and lofl_DPLL3 cleared.

In the .tcs file, according to the output, the source is PPL2 for OUT0, isn'it?

When I connect 10 MHz to the IN0 or 1, the lopl_DPLL3 lofl_DPLL3 are locked after 1 second.

Does we have to wait more time ? 

Regards,

Patrice