LMK1D1204: design review

Nandini Muralidharan

Part Number: LMK1D1204

Tool/software:

Hi,

Can you please review the attached schematics and provide feedback?

LVDS Output of the clock buffer feeds to a FPGA with below LVDS characteristics. Are the termination resistors given able to support the input LVDS voltage requirement of the FPGA?

TI_DDR_Clkbuffer.pdf

Thanks

11 months ago

0 vicente flores prado 11 months ago

TI__Mastermind 29172 points

Hi Nandini,
LMK1D1204 meets input spec.
Refer to image below.

LVDS driver is typically DC coupled to LVDS Rx.
Pin 8 should be connected as follows:

I am unsure of what the resistors are for?

The output should be DC coupled to the receiver - this is the easiest implementation

Regards,

Vicente

0 Nandini Muralidharan 11 months ago in reply to vicente flores prado

Intellectual 810 points

Hi Vincente,

For DC-coupling between LMKD and FPGA, what is required?

For example, do we need to have any resistor in Series between LMKD and FPGA? Or just a 100-ohm parallel termination between P&N?

Also pin8 description seems to be for AC-coupling. How should the pin be handled in case of DC-coupling?

0 vicente flores prado 11 months ago in reply to Nandini Muralidharan

TI__Mastermind 29172 points

Hi Nandini,
Refer to snippet below found on page 13 of DS:

Pin 8 or Vac_ref1 is the bias voltage pin - this pin requires a 0.1uF cap to GND in the case the that input is AC coupled but in the schematic it is not.
One more recommendation, the 100Ohm differential termination for Clkin - just remind customer to place near input pins.

Best regards,

Vicente

0 Nandini Muralidharan 11 months ago in reply to vicente flores prado

Intellectual 810 points

Hi Vincente,

Based on oscillator datasheet:
VOS = 1.15V to 1.35V
VOD = 250mV to 450mV

From LMKD buffer input details
VICM = 0.25V to 2.3V
VINDIFF = 150mV (for single ended)

Based on these values, Can you pls confirm that LMKD can be DC-coupled with input clock?
If yes, how should Pin8 of LMKD buffer be handled?
Also by "the 100Ohm differential termination for Clkin", I hope you mean the input pins of FPGA receiver. Correct?

0 vicente flores prado 11 months ago in reply to Nandini Muralidharan

TI__Mastermind 29172 points

Hi Nandini,
Yes LMK1DB can be DC coupled with this reference.

VAC_ref can be float since AC coupling of the inputs is not required.

No the 100ohm differerntial termination on the CLK input side of the buffer. This should be near the LMK1D pins.
Refer to image below.

Best regards,

Vicente

0 Nandini Muralidharan 11 months ago in reply to vicente flores prado

Intellectual 810 points

Understood Vincente.
We will keep the VAC_ref pin NC and keep the 100ohm near LMKD inputs.

Thank you

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LMK1D1204: design review