Tool/software:
Dear Forum and Support teams,
Regarding the phenomenon described, could you provide your insights on the possible causes and suggestions for mitigating the symptoms?
Description of the phenomenon: When outputting a 1148.375 MHz clock from the TRF3765 as the sampling clock for the ADC (AD12J1600) and acquiring A/D converted data, the phase of the data shifts by approximately 12 degrees when re-acquired after a 30-minute interval from the first acquisition. Additionally, it has been confirmed that the phase shifts by about 0.3 to 0.6 degrees over an interval of about 1 minute, indicating a gradual rather than a sudden change.
During data acquisition, the PLL lock is not disengaged, and the system appears to be operating normally with no apparent issues, leading to the hypothesis that the phenomenon might be due to the accuracy of the PLL lock.
The design values for the TRF3765 are as follows:
FIG1
Kind regards,
Kato