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I want to know what is the limit on the distance between the IC and the device when we are in layout? I know that the closer the better, if it is 7.2mil, will it be too far?
That is not an easily answerable question. I do not know what the width or shape of your traces are, nor do I have your board to be able to test. However, you can perform signal integrity simulations to determine what the slew rate and swing you will have at that distance from the IC, and as long as all of the clock input characteristics in the datasheet are met (see page 7 - I am assuming you are sending a clock signal from the IC to the CDCDB2000), then that distance is acceptable.
