Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State
  • Replies 4 replies
  • Subscribers 21 subscribers
  • Views 105 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

SA555:The deviation between the output cycle with load and the design value is too large

qingmei wen
Prodigy 10 points
Part Number: SA555

Tool/software:

Why is there a significant deviation between my design cycle and the cycle after being loaded without a steady state? What could be the reason for this
The following are my design values (without load, the reading value of the oscilloscope is basically consistent with the design value)
TH (High Level Time s)=0.693 * (1.2M Ω+10M Ω) * 100nF ≈ 776.16 ms
TL (Low Level Time s)=0.693 * 10M Ω * 100nF ≈ 693 ms
T=TH+TL ≈1.46916 s
After adding the load, as shown in the figure
The circuit principle diagram
  • 0
    Prodigy 10 points

    The circuit principle diagram

  • 0 in reply to qingmei wen
    TI__Guru*** 149206 points

    Qingmei,

    qingmei wen said:
    (1.2M Ω+10M Ω)

    Where is the 1.2M ohm resistor? Can you turn off AC coupling on the output waveform.  If output cycle time changes when a load is applied then I expect output current is high and gets back to the timing. Does that cause pin 8 & 4 to be too variable?  How about the grounding, is waveform for pin 1, C3 bottom, C4 bottom the same?  It should be useful to check waveforms for pins 5, 2+6 too.

  • 0 in reply to Ron Michallick
    Prodigy 10 points

    Hello 

    1、1.2M ohms at R3 position

    2、Ac coupling off，

    No load

    loading

    3、current13mA，

    4、is waveform for pin 1, C3 bottom, C4 bottom same。

    5、 ，Why does C1 electrolytic capacitor affect the cycle

    example：When C1 is not added, the cycle is 0.9s, and after adding C1, the cycle is 1.2s,Can you help me analyze why this is,thank you.

  • 0 in reply to qingmei wen
    TI__Guru*** 149206 points
    qingmei wen said:
    When C1 is not added, the cycle is 0.9s, and after adding C1, the cycle is 1.2s

    For SA555, VCC voltage does not affect timing provided that VCC voltage is constant throughout out the timing cycle. With a [50/60 * 2] Hz signal on C1, VCC voltage will not be constant over a second and a half. This is even more true with C1 removed. 

    One way to make SA555 voltage more constant is to move RB1 to be between C1 and ZD1 and increases voltage rating of C1. 

    I see a timing glitch on no load waveform.  Add a100nF cap close to SA555 power pins.