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LMK1C1103: Does the clock buffer's output follow the input in respect of rising and falling time?

Part Number: LMK1C1103

Tool/software:

Dear Friend

I want to reduce rising and falling speed of the clock for EMI/EMC purpose by putting a ferrite bead in series with buffer's output.  instead of adding ferrite bead for each clock, I am think just adding one ferrite bead at input of the buffer.  But I am not sure if the buffer's output will exactly follow the input in respect of rising and falling edge timing, or the buffer has some re-timing feature hiden.

please advise.

Thank you.

Tony

  • Hi Tony, 

    It won't be exact, but the difference is minimal- - there is some propagation (input-to-output) delay and for LMK1C11xx family it can be up to 3ns. 
    This value does vary depending on VDD so if for example you plan on utilizing a 3.3V VDD the maximum prop delay is reduced to 2ns. 

    There is no retiming feature in this device - all outputs should be close in phase and following the input. 

    Best regards, 

    Vicente