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Original question:

LMH1983: Questions about LMH1983

LMH1983: Regarding the lock time of LMH1983

user6438649
Intellectual 400 points
Part Number: LMH1983

Tool/software:


To whom it may concern

I have a few questions about LMH1983.

The LMH1983 has a NO_LOCK signal that indicates the LOCK state.
I would like to know the maximum number of seconds this NO_LOCK signal will be asserted 0 from 1.

Question 1: In the evaluation board configuration, if the format is NTSC, 525i, how many seconds will the NO_LOCK signal appear after?

Question 2: I think there is a relationship between the bandwidth and the lock time. Can you tell me the formula for this relationship?

Best regards,

  • +1
    TI__Guru** 107910 points

    Hi  Doi-san,

    Loss of lock is determined by registers LockStepSize and Loss of Lock Threshold. Assume LockStepSize is setup properly then when the number of H-sync cycles as defined in Loss of Lock Threshold is reached, then NO_LOCK will turn HIGH. 

    As a rule of thumb, the PLL lock time is approx. equal to 4/loop bandwidth. For example, if the loop bandwidth is 10Hz, then the lock time is approx. 0.4s. However, when cycle slip happens, the actual lock time would be much longer. Cycle slip may happen when the phase detector frequency is much higher than the loop bandwidth. According to Table 2 in the datasheet, the lowest phase detector frequency is 4.4955kHz while the highest is 67.5kHz, they are much greater than the loop bandwidth (typical is 10Hz).