Tool/software:
Greetings.
I am trying to configure LMK04828 to use a 100 MHz oscillator connected to OSCin (bypassing the CLKin inputs entirely) to generate 100 MHz clocks on all DCLKoutX pins.
The issue is that PLL2 is not achieving lock. Consequently, some outputs (e.g., DCLKout6, DCLKout8) are defaulting to incorrect frequencies in the 300-312.5 MHz range instead of the target 100 MHz.
My loop filter design for PLL2 uses the following components:
-
C1 = 56 pF
-
C2 = 1.8 nF
-
R2 = 820 Ω
The register configuration was generated using TICS Pro. What are the critical settings I should double-check for this OSCin-bypass mode to ensure PLL2 can lock correctly? I'm programming the chip from Zynq MPSoC FPGA using SPI (CS,SCLK,SDIO). After writing each register (24 bits), I make CS High & while writing, I make it low.
Thanks in advance!
- Srujan
