CDCE72010 Lock on ADS62p48 EVM (Rev. C)

Hi Aaron,

These divider setting changes look okay and should not cause any issue. Can you share your loop filter component values and your schematic for the VCXO input termination? One possible cause for the PLL not locking could be an unstable loop filter. In these settings I noticed also that the VCXO input termination is not enabled which should be okay if the input is terminated properly on the board.

Best regards,

Matt

Hello Matt,

Thanks for the quick reply. The schematic can be found on page 3 of the ADS62PXX-EVM schematic (http://www.ti.com/litv/zip/slar050). The loop filter components are as follows:

CP_out -> 0.1uF -> GND

CP_out -> 7.15K-Ohm -> 22uF -> GND

CP_out -> 1K-Ohm -> V_CTRL

V_CTRL -> 0.1uF -> GND

The VCXO is the VS-705 at 320MHz. According to the CDCE72010_PLL_Calculation_V1.08.xls these values provide phase margin of 78deg so it should be stable.

I'll check the termination issue.

-Aaron

Hello again,

The VCXO input is terminate on board with LVPECL DC termination. Thus I have disabled the internal termination.

I suspect that the issue is with the PRI_REF clock. When I remove the primary reference cable the lock LED flashes. I have now connected the ref input to a waveform generator and tried various inputs (sine, square) at different levels. Nothing seems to work. The lock LED will flash once in a while when adjusting the level of the generator causes some switching to occur within the generator.

Is the PRI_REF termination on the ADS62PXX-EVM correct? It has series 10nF cap connected to 10k-Ohm resisters tied to VCC and GND. I would like to drive this with a transformer coupled clock in the design and need a 50-Ohm termination.

-Aaron

... an update.

I hooked up a waveform generator to the PRI_REF input. I am able to get the device to lock when providing a reference of 5.716MHz rather than 10MHz. I have quadruple checked my divider settings. Any ideas?

Current settings are:

regSettings = [ ...
    '002C024'; ... 0
    '8380000'; ... 1
    '8340000'; ... 2
    '8340000'; ... 3
    '8180000'; ... 4
    '8180000'; ... 5
    'EB04000'; ... 6
    'EB04071'; ... 7
    '010C01D'; ... 8
    '6900004'; ... 9
    '00FC03F'; ... A
    '8000358']; %  B

... checked yet again the feedback divider. This was wrong... changed to:

 '80001D8']; %  B

and can now lock with input reference between 10.0037 - 10.0009 MHz.

almost there...

-Aaron

Hi Aaron,

Were you able to get everything working well?

Matt

Hello Matt,

I was able to get it to lock by increasing the lock detect window size. Now it locks nicely to my original 10MHz reference. I wonder if I would be able to achieve the same by adjusting the phases at the PD input. Currently both phases are set to 0.

-Aaron