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LMK04828: clock configuration in Uboot on AFE8030 EVM

vamsi bolla
Prodigy 20 points

Part Number: AFE8030EVM
Other Parts Discussed in Thread: LMK04828, AFE8030,

We are configuring LMK04828 from Linux and U-Boot in an Agilex + AFE8030 setup.

LMK configuration from Linux works and AFE relink succeeds.
But when configuring the same LMK registers from U-Boot using sspi,it is not locking and even returning FFFFF.

In Linux flow, we perform:

->I2C pre-sequence->CPLD unlock ->SPI mux switch to LMK ->LMK SPI writes ->SPI mux switch back to AFE

Is there any additional timing/reset/PLL lock/SYSREF sequence required when configuring LMK04828 from U-Boot?

image.png

  • 0
    TI__Guru* 82695 points

    Hi Vamsi,

    Please advise on the AFE8030 EVM, how the SPI connection from the Agilex FPGA kit to the AFE8030 EVM FMC connector to the LMK04828 SPI are routed. This will help our clocking team to better support you.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Hi Kang,

    The SPI routing is:

    Based on our software flow, SPI access appears to be routed through CPLD/mux logic toward the LMK04828 on the AFE8030EVM.

    In Linux:

    • SPI device used is /dev/spidev1.0
    • LMK04828 programming succeeds
    • Both PLLs lock
    • AFE relink succeeds

    Sequence used:

    1. HPS I2C pre-sequence
    2. CPLD unlock
    3. SPI mux switched to LMK04828
    4. 136 LMK registers written over SPI
    5. SPI mux switched back to AFE8030

    In U-Boot:

    • Same I2C/CPLD/mux sequence is executed
    • Same LMK register values are sent using sspi
    • But SPI transactions return FFFFFF
    • LMK does not fully lock
    • JESD relink later fails with PLL Loss of Lock / Link Not Up errors

    From Linux logs and behavior, SPI communication to AFE8030 itself appears functional, but the LMK SPI path from U-Boot may not be matching the Linux SPI transaction format/timing.

  • 0 in reply to vamsi bolla
    Prodigy 20 points

    Hi Kang,
    can you help me with this?