How do I disable the VLDO output pin on the CDC3RL02? We are not using this pin and would like to make sure we either leave it floating or terminate it correctly. Per the datasheet:
"When disabled, the device enters a low power shutdown mode consuming less than 1 μA from the battery. The LDO requires an output decoupling capacitor in the range of 1 μF to 10 μF for compensation and high frequency PSR. Thisc apacitor must stay within the specified range over the entire operating temperature range. An input bypass capacitor of 1 μF or larger is recommended."
Does this mean we should place a capacitive load regardless of whether then LDO output is being used? If so, what is the recommended cap value outside of something larger than 1uF? I assume any LDO oscillation will affect the buffer performance?
