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LMK03000C

twan hooft
Prodigy 155 points
Other Parts Discussed in Thread: LMH1983, LMK03000, CODELOADER

We have designed a board with uses a LMH1983 from national and we use this as an input to the LMK03000

We AC coupled the inputs and have a differential swing of 800 mV and a frequentie of 148.35 or 148.5 Mhz .

and the LMK03000 give's it a DC offset of 1,5 Volts

(When we set PLL_MUX to 1 and 2 we kan toggle the LD pin manually)

We want to use the LD pin to test the input and the interal ref.

$port.WriteLine("[0x80 0x00 0x04 0x00]")  //reset

$port.WriteLine("[0x00 0x00 0x04 0x00]") //output 0 off

$port.WriteLine("[0x00 0x03 0x05 0x01]") // only output 1 is turned on : CLK_MUX =DIVIDED

$port.WriteLine("[0x00 0x00 0x04 0x02]") //output 2 off

$port.WriteLine("[0x00 0x00 0x04 0x03]") //output 3 off

$port.WriteLine("[0x00 0x00 0x01 0x04]") //output 4 off

$port.WriteLine("[0x00 0x00 0x04 0x05]") //output 5 off

$port.WriteLine("[0x00 0x00 0x04 0x06]") //output 6 off

$port.WriteLine("[0x00 0x00 0x04 0x07]") //output 7 off

$port.WriteLine("[0x00 0x82 0x80 0x0B]") // DIV4 = on

$port.WriteLine("[0x02 0xA5 0x00 0x0D]") // OSC freq = 148  // VCO_R4 =0 //VCO R3 = 0 //VCO C3 C4 =0

$port.WriteLine("[0x18 0xB0 0x04 0x0E]") // Fout is ena // ENA Global CLK out // PLL_MUX = 0x09 // PLL_R = 0x04

$port.WriteLine("[0xC8 0x00 0x10 0x0F]") // CP_GAIN =3 // VCO_DIV = 2 // PLL N = 0x10 =16dec

I expected to see 148.35 / 4 = 37.0875 Mhz / 2   = 18.543Mhz on the LD pin.

When I measure this there is a Low signal.

kan any one help me out

  • 0
    TI__Mastermind 32575 points

    Hello,

    Is the input clock stable and at the correct frequency before the LMK03000 is programmed?

    Does the clock output or VCO output operate at the correct frequency?

    Regards,

    Alan

  • 0 in reply to Alan O
    Prodigy 155 points

    Hi alan

     

    thanks for your response

     

    Yes my input clock is stable before programming the chip.

    There is no output clock on the output.

    The F out give a  freq that seems to be  1.2 Ghz

     

    Yesterday I discoverd that the R divide/2 (and also N divide /2 ) on the LD pin  IS WORKING  when EN_CLKout_Global is set to zero. !!!! (weard) 

    The R divide/2 = 18,5... Mhz , the N divide/2 = 17.9... Mhz so this is close but also no lock.  

  • 0 in reply to twan hooft
    Prodigy 155 points

    hi alan

    do you have any futher idea's for me ?

  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Can you please confirm that your MICROWIRE timing is compliant with the datasheet specs?  While it seems the device is responding to your programming settings, I want to be sure device programming is not the issue.

    What are your external loop filter values (R2, C1, and C2) connected to the CPout pin (corresponding to Figure 10. Loop Filter in the datasheet)? 

    Even better, could you please share an image of your application schematic for review?

    Thanks,
    Alan

     

  • 0 in reply to Alan O
    Prodigy 155 points

    Hi alan

    I have a few files ready for you

    2 of the micro wire interface.

    and 1 schematic where you also can verified the LOOP filter.

    The input on the schematics is not AC coupled. On the chip I am testing it is AC coupled with 100nF.

    I removed all components that are connected to LVDS or LVPECL outputs. to have a good test.

    how can I get the files to you ?

  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Hi Twan,

    The schematic image quality is not good and I can't read any text.  Can you please send a higher quality version?

    Regards,
    Alan

  • 0 in reply to twan hooft
    Prodigy 155 points

    as promised a better schematic view. Remember I already use a AC coupled input. and disconneced all outputs for the tests.

    GENLOCK_LT.pdf
  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Hi Twan,

     I reviewed the schematic…it seems OK.

     Please advise:

    1. Can you confirm that the SYNC* pin is not asserted?
    2. Are all three LMK03000 not able to lock, or just one of the devices?  How many boards have this issue, and does it occur consistently?
    3. Have you verified the SPI signals from the Freescale uP are compliant to the uWIRE timing requirements for LMK03000?  I’m also curious why LE signal goes low much earlier (almost 2 ms before) than CLK/DATA are toggled.

    0160.LMK03000C_AXON.ppt

    From your scope photo in Slide #1 in the attached PPT file, it seems at least one DATA bit may be occurring before the CLK rising edge (as circled in red). 
    I cannot tell if you’re meeting the uWIRE CLK/DATA timing requirements because time scale is large relative to the CLK/DATA timing, and I don’t know the register data you intended to write.

    Could you please re-try the scope captures for CLK, DATA, and LE signals by zooming into each byte (4 bytes per register) and overlay the register address/data bits you intend to write?

     Also, I mapped your original register settings to CodeLoader GUI to understand the device configuration.  See Slides #2-5.
    Do the GUI settings below match your expectation/requirement?

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 155 points

    hi alan

     

    Thanks for the detailed look at my disign.

     

    I ordered a demo board of the lmk03000 and modified the Loop filter on the demo board to my needs and give it the same input as my not working design.

    I downloaded all parameters with the codeloader. (same settings as you) . and It worked perfectly !!!!!

     

    So I disconnected the uWIRE interface ( buspirate that i disigned) . And connected the parralel national uWIRE cable to my own  design.

     

    No succes. The chip is reacting strange but consistant(as before). and still will not look to the input( measured on LD pin = set to N divider)

    on the LD pin = 4,6 Mhz

    Is it possible to have a conversation by phone ?

    Twan.van.hooft@axon.tv

     

    answers to your questions

    1. SYNC is pulled with 10k to VCC.

    2. non of the 3x LMK03000C on my board are working. also another proto board did not help. also changing the chip did not help

    3.Yes I rechecked this. and already post a detailed view of the uWire. To be sure I connected the uWire interface cable from national to my design. and programmed the device with CODELOADER.

     

  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Hi Twan,

    Some other ideas on things to check:

    1. DId you confirm that all Vcc pins of the device are all 3.3V +/- 5%?
    2. What is the loop filter voltage (CPout pin)?  If you use a high impedance o-scope probe, what do you see?
    3. Have you tried to use your buspirate interface to program the LMK03000 EVM? 

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 155 points

    Hi alan

     

    1) the power supply is 3.277 +- 20 mV rimple

    2)The loop filter is low. at gnd level

    3) yes I tried the buspirate to the LMK03000 EVM. It all works like I it should.

     

    could there be a component problem in a batch ?

     

  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Have you tried reflowing the device (or replacing the suspect device) and re-checking all pin voltage levels are as expected?

    Can you please share your PCB layout so I can check it?  I can view Cadence Allegro or Altium files.  PDF print with layers on separate pages may also work.

    If nothing turns up after these, then maybe you can submit the devices for PQA/failure analysis.  Alternatively, you may also try desoldering the suspect device, mounting it to the EVM and check for the issue?

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 155 points

    Hi alan

    I have made screen shot of the PCB area. I hope you can sea enough but I understand that you dont know what all signal are. I am not going to post our design here. but I like to sent it directly to you when I know your email adress. it designed in altium. 

    The change of chip of the eval board will be done this friday. so you hear from me again

    Bottom.zip
  • 0 in reply to twan hooft
    Prodigy 155 points

    Hi Alan

     

    After a very long search we found a problem.

    It seems to be that the Uwire bus is very sensitive and generates spike's on the data wire signal.

    As we added the voltage divider used on the demo board we are able to work ok with the lmk03000 chip. The voltage divider on the demo board has very high ohmed resistors.

    What was the reason for TI to to this ?

    Will this always work in this configuration ? also whit more components in the uWire bus !

    why is this not in the data sheet ?

    Does TI know what is going on in the chip because of the spikes ?

    Why does the register for setting LD pin high or Low always work correctly and other one's doesnot ?

     

     

     

     

  • 0 in reply to twan hooft
    TI__Mastermind 32575 points

    Hi Twan,

    Glad you found the issue. 

    Were the spikes on your DATA input signal causing it to violate the VIH and/or VIL spec limits for MICROWIRE interface in the datasheet?

    What is causing the spikes in the first place (perhaps signal integrity / reflections)?  Perhaps the driver's output current/drive strength is too high and needs to be reduced, and/or maybe impedance matching is needed to manage signal integrity.  Are you using series termination after your driver and 50-ohm characteristic impedance traces? 

    The LMK03000 eval board used voltage dividers (~0.64) only to attenuate 5V TTL/CMOS logic levels from parallel/LPT ports in older PC's (legacy support).  Even if 3.3V logic level inputs were used (such as from the USB2UWIRE interface board), the logic high level (2.1V = 0.64 x 3.3V) still meets the VIH min spec of 1.6V.  This voltage divider should not be required if the input signals comply with the MICROWIRE input specs in the datasheet.

    Regards,
    Alan