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LMK04808 input frequency

Daniel Eriksson84
Prodigy 20 points
Other Parts Discussed in Thread: LMK04808, CLOCKDESIGNTOOL

Hi,

I'm wondering about the lower end frequency for the inputs to LMK04848.

We're using the LMK04808 with dual PLL and internal VCO.  PLL1 is set up to compare CLKin0 and CLKin1(FEEDBACK_MUX = FBCLKin). We divide the CLKOut down to about 1kHz and feed back to CLKin1/FBCLKin. CLKin0 is a reference of also 1kHz.

the problem is that PLL1 is not locking so I'm wondering if the frequency is simply too low? we've tried 68kHz as well with no change.

  • 0
    TI__Mastermind 32575 points

    How are you determining that PLL1 is not locking?  Are you looking at the output clock w.r.t. the input clock (not phase locked and stable), or are you using the PLL1 DLD lock status output?

    Are you evaluating on the device on the LMK04808EVM or on your own application board?

    Have you used CLOCKDESIGNTOOL to design your N/R divider ratio and loop filters for PLL1 and PLL2, and make sure your PLL loop design has sufficient phase margin?  With 1 kHz PFD frequency, your loop bandwidth should be designed to be lower than 100 Hz.

    Note that with low PLL PFD of 1 kHz, the VCXO input impedance (if low enough) could cause enough leakage on the Vtune (CPout1) line and affect actual PLL lock or prevent proper DLD lock detection.

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 20 points

    THanks for the help :)

    Putting an opamp on CPout1 to boost the signal solved it.