LMK04828 improve DS values

Atmeg

In DS at pg. 80 there is ambiguous definition of PLL1_N divider value: should it be 12 or 14 bits wide?

0 Timothy T over 9 years ago

Hello,

Thank-you for pointing this out. PLL1_N should be 14 bits wide as CLKin2_R just above it.

0x3fff is the max value of PLL1_N[13:8] combined with PLL1_N[7:0]..

73,

Timothy

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