CDCM7005-sp phase noise question

Dave,
after double check our CDCM7005 database I realized that we have no phase noise data for the range of 1GHz available. We can plan for specific measurements if required and if details for setup are available. I assume it is PLL bypass or is even a 1GHz VCXO connected?

Siggi

Good morning Siggi,

I have a VCXO (QT725S) connected to the PLL currently.  I can supply the SPI data if that is helpful, I don't have that in front of me right now unfortunately. 

Dave

Hi Siggi,

To follow up, I am using the following words to program the CDCM7005-SP:

W0:  0001801C

W1:  0000006D

W2:  DB7014A2

W3: 00000027

Dave

Siggi,

Are you planning on publishing 1GHz phase noise data?  Please advise.

Dave

Dave,

I figured out that we have no comparable 1GHz source to your VCSO available. Because we can not extrapolate phase noise from lower frequency we are not able to provide your requested data yet. I think about to measure noise floor above 10MHz offset to get a reference point. What offset frequency range is in your interest? To get a real conclusion we would need your source as reference.

Siggi

Siggi,

I would like to get as close to the fundamental as possible, 100Hz would be good. 1kHz is acceptable.

Can't you use a 1GHz source that you have on hand, examine the jitter of that source. Then apply it to the CDCM7005 and examine the output of the LVPECL differential? Once you have both jitter values, you can back calculate the contribution of the PLL, no?

Dave

Dave,

 

Yes you are totally right, this the right approach to determine the jitter contribution of the PLL. This works if the supplied source shows a better performance than the PLL. Otherwise we just measure the performance of the supplied signal. In this case I focused on offset frequencies starting at 100k and above. In this range our source is already worse than your VCSO with the result that we are not in the range I assumed you expected. Attached is the performance of the source I plan to apply. This is a generator signal and can just be measured in buffer mode to get a feeling where we are. But I still not know if it is better than our device. The measurement will be delayed because I need to wait for a timeslot for the equipment. New silicon arrived in our lab and has priority.

 

Regards,

Siggi

 

Hi Siggi,

That is very comparable to our source, thank you for sending that to me.  I look forward to seeing what you get out of the PLL, thanks for taking the time to put this together.  Not trying to rush you, when do you think you'll have time to run the actual test?

Dave

Dave,

Following screenshot shows the typical 1GHz input and output (LVPECL) signal of CDCM7005. (This is captured in buffer mode only. Input source is a signal generator and not capable to run in PLL mode.) Till 300k the output performance follows the input signal. This means the CDCM7005 has a better performance as indicated in the curve but we are limited to the input signal to determine the real performance. >300k we see the addition of the CDCM7005. In PLL mode and equivalent setting same performance can be achieved.

Regards,

Siggi

Hey Siggi,

I didn't see anything attached, could you resend please? 

Dave