CDCLVD2102 minimum input freq

ACGUY

Other Parts Discussed in Thread: CDCLVD2102

Hi all,

Please let us know how much the minimum input freq of CDCLVD2102.
Customer will use this device for data and clock buffer.
Conditions are as follows;
- Input signal, LVDS
- Data rate, 600Mbps (max)
- Data width, 10bits (Not all High /Low)
- Synchronous clock, 300MHz

Can this device to support non-contiguous 0 or 1 data pattern ?

Regards,
Nagai

over 9 years ago

0 Alan O over 9 years ago

TI__Mastermind 32575 points

The device operating frequency supports down to DC (static high or low state).

Does the data pattern have DC-balanced line coding? If not, then the input signal should be DC-coupled to the input buffer of the device.

Regards,
Alan

0 ACGUY over 9 years ago in reply to Alan O

Guru 11170 points

Your advice is very accurate!
Many thanks!
Nagai

0 Liron Rodavsky over 8 years ago in reply to Alan O

Prodigy 190 points

So if I am using LVDS standard as input to the buffer (with no caps) the data does not have to be DC balanced correct and then I can transfer also data rather then clock. Correct?

Clock & timing

Clock & timing forum

CDCLVD2102 minimum input freq