cdce72010

duuk lee said:

1).  What does "jitter cleaner" mean ?  ( Does this mean its output jitter is determined by its VCXO, instead of reference clock input, or something else ? ) 

You are correct.  Jitter cleaner is something of a marketing/intended use term.  As technically any device with a VCO/VCXO is a jitter cleaner, but when using a VCXO, typically very narrow loop bandwidths can be designed which still result in jitter being reduced even a low offsets.  Unlike a VCO which may have higher than reference noise at low offsets resulting in a jitter dirtier... but a VCO will still clean jitter for higher offsets!

duuk lee said:

2). What would be its equivalent jitter value, for table 1 on page 18 ?  ( Those phase noise is equivalent to 0.5ps - 1ps jitter, or some other values ?)

There are several values, I might for the /1 LVPECL I get 232 fs rms jitter from 10 Hz to 10 MHz.  Tip, download the CLOCKDESIGNTOOL software, open any device.  Change the first OSCin (or CLKin block) to the frequency of interest, click the phase noise graph button on the OSCin.  You can then enter custom phase noise values, set your integration range, and get the resulting jitter.

I wouldn't be surprised if the others a a bit higher, the noise floor at lower frequency tends to not scale down as fast (typ 10 dB/dec) as VCO and PLL noise (20 dB/dec).

duuk lee said:

3). So it requires external  XO circuits and PLL loop filter on the PCB ?

Correct, you need an external loop filtter + VCO or VCXO on the PCB.  As with all PLLs, you need your external reference also.

73,
Timothy