LMX2571 Lock Problem with MULT Setting

Hi Ufuk,

We received your question. Thank you for your interest in our products. I forwarded your query to the applications engineer most familiar with this device.

Best Regards,
Julian

Hi Ufuk,
Would you provide screen shots of your configuration?

Hi Noel,

Sure. I have put it below. I also put the loop filter characteristics of the custom board.

As I said before, I have also tried the same setup with evaluation board with its own loop filter circuit given in the datasheet. I used different charge pump current values and nothing changed.

I am waiting for your reply.

Best,

-

UT

Hi Noel,


Thank you for the reply. I have worked on this today and I realized some different things on LMX2571. With your setting, I could also make it lock by using evaluation board with code loader. And then I tried this with microcontroller and everything was fine. But when I tried different frequency like 140MHz. It failed and did not work. Once I was trying to make it lock. I have figured out that if PLL is locked with some setting ( say for example with MULT = 4 ) you can make it lock with MULT = 6 succesfully after locked with MULT = 4. I had tested my operating freqeuncy band with MULT = 4 and it had worked succesfully for all channels. Hence I changed my code in microcontroller so it first locks with the setting MULT = 4 and then it sets MULT = 6 and locks in the desired channel. This is interesting but it worked in my application. Still I am wondering why is that so and can it be better solution for my application?

Thank you for the service,

My best,

-
Ufuk

Hi Ufuk,
Whenever you change the PLL settings (except for output dividers, they are outside the loop), you need to calibrate the internal VCO by sending R0 with FCAL_EN=1. For example, if you are locking to 480MHz and then you want to lock to 520MHz so you program a new N-counter value. If you stop here, the PLL will not lock because the VCO is not calibrated. Now, program R0 again (assume you already have FCAL_EN=1) and you will get it locked.

Hi Noel,

I knew what you have suggested to me. In my frequency setting, if MULT and N counter values are changed, registers are programmed in order (first R6 and then R4 and lastly R0 with FCAL_EN = 1). However, even in this situation, I cannot make PLL locked to the 140MHz with your suggested settings. The interesting thing is that I can make it work, if I first lock 140MHz with MULT = 4, it locks and then I reprogrammed with MULT = 6, and correspongind Ncounter and lastly R0 with calibration enabled. I learned that PLL locks everywhere in my operation band (between 130-180MHz) with MULT = 4, however it does not work with MULT = 6. But if you first lock PLL with MULT=4 to the frequency where it does not work with MULT= 6 and then change MULT it keeps locked. Is this result reasonable or do I make some wrong operations? Does this PLL has to lock in my operation frequency band with MULT = 6 directly just by changing the corresponding N counter and calibration enabled ?

As I said you before, all frequency settings are programmed to the registers in order and R0 is programmed lastly with calibration enabled.

Best,

Hi Ufukt,

Would you advise which frequencies you cannot lock with MULT=6? I would like to give it a trial.

Hi Noel,

As I said before, for example, I cannot make it lock at 140MHz. I tried both lower frequencies like 136MHz and upper frequencies (145MHz) and all of them were failed.

However, with the same loop filter settings, if the PLL is locked first with MULT=4 and then locked with MULT = 6. It is locked in all frequency band of interest.

Hi Ufuk,

Please try with Prescaler equals 2, it should work now.

Hi Noel,

Prescaler should be set to 4 in my application to obtain desired maximum fm deviation. Otherwise I will get half of it. Actually, I can make PLL locked in all frequency band of interest with my method even when Prescaler = 4 (first lock with MULT = 4 and then lock with MULT = 6). But this is very interesting and I have no idea why this works?

Hi Noel,

Thank you for the reply. It is really interesting that your suggestion works successfully. Could you explain it more about setting this hidden register bit high? What does it actually do? Is there any trade-off using this bit (any disadvantage)?

Since I can make it work without using that bit by manipulating in software.

Best,

Hi Noel,

Thank you for the explanation. I am looking forward to next revision for any other updates.

Best,