CDC3RL02 circuit review with clock buffer enable always

Jung-Ho Seo

Expert 5425 points

Dear Experts,

To clock buffer output enable always, Is it okay to tie CLK_REQ pin to VLDO pin directly ?

I doubt it because VLDO is enabled by CLK_REQ.. Would you confirm to me ? Thanks,

over 8 years ago

0 Jung-Ho Seo over 8 years ago

TI__Expert 5425 points

Hi,
What I doubt is that VLDO is enabled by CLK_REQ..
So, I think there is possibility not to trigger VLDO to be high at power ON . Once triggered, both outputs are always ON state.
Do you understand what I doubt ? would you clarify me again ?
Thanks,
JH Seo.

0 Jung-Ho Seo over 8 years ago in reply to Jung-Ho Seo

TI__Expert 5425 points

Hi Alan O,
WOuld you answer to me again on upper question ?
THanks,
JH Seo.

0 Alan O over 8 years ago in reply to Jung-Ho Seo

TI__Mastermind 32575 points

Yes, you are correct. The LDO output is enabled by OR-ing of both CLK_REQ inputs, so these inputs should NOT be pulled up through VLDO. They should be pulled high to the valid Vih level to enable the outputs. Sorry, I missed the OR-gate in the block diagram. This is also explained in section 9.2 of the datasheet.

Alan

0 Jung-Ho Seo over 8 years ago in reply to Alan O

TI__Expert 5425 points

Thanks for confirmation..

Clock & timing

Clock & timing forum

CDC3RL02 circuit review with clock buffer enable always