LMX2594: LMX2594

Wenjia Tang

Part Number: LMX2594

I need to generate two frequency at 5GHz, and 9.5GHz. My question is if I using 50MHz as input reference clock. Will the performance degrade if compared with 100MHz reference?

over 7 years ago

0 Brian Wang over 7 years ago

TI__Expert 8505 points

Wenjia,

Where this matters is the Fpd frequency. Theoretically the higher this is, the lower the N value (which is Fvco / Fpd), which relates to the PLL floor phase noise. With your example, the PLL floor phase noise will be 3dB better for the 100MHz reference compared to the 50MHz reference. Do you have a phase noise spec at an offset you are close to and trying to beat?

regards,

Brian Wang

0 canberk unal over 7 years ago in reply to Brian Wang

Prodigy 150 points

Dear Brian,

Will the phase performance degrade if the reference clock is lower with the same PFD frequency. For example if we use 50MHz reference clock and multiply it to get 100MHz PFD frequency in LMX2594(LMX2594 has multiplier in the input stage) , or we use 100MHz reference clock without multiplication to get 100MHz PFD. Should we expect any phase performance difference ?

0 Brian Wang over 7 years ago in reply to canberk unal

TI__Expert 8505 points

Wenjia,

Good question. The PLL floor phase noise is dependent on the PFD frequency so given the same 100MHz PFD they should be the same. Note you have two ways of doing this:
1. use the input doubler (register name: OSC_2X), this is a very low noise doubler than doesn't contribute to additional noise on the PLL floor
2. use the Multiplier (register name: MULT), this circuitry does add alittle noise though, so it may have about 0.5-1dB higher PLL floor noise than if using the input doubler.

Regards,

Brian Wang

Clock & timing

Clock & timing forum

LMX2594: LMX2594