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CDCI6214: Recommended EEPROM Procedure

li wang
Prodigy 30 points
Other Parts Discussed in Thread: CDCI6214

Hello Stan,Patrick,

SETP1 RESETN 0
SETP2 RESETN 1
SETP3 by floating refsel and eepromsel   put the device into Fall-Back MOD
SETP4 Program register addresses in descending order from 0x44 to 0x00 including all register addresses

What kind of operation is done next can make the chip work  fine？

  • 0
    TI__Expert 5325 points

    Hello Li,

    I took the liberty of splitting your question to a new thread.

    When you have a new unit, there are two ways to re-program it to your desired configuration:

    a) Start the Unit in "fall-back" Mode, so that the I2C interface is active and you can overwrite the EEPROM content according to your requirement. After a power cycle the new configuration loads from the EEPROM and you are "good to go".

    b) By default units are shipped with "page 0" config with I2C disabled and "page 1" with I2C active. Therefore you have to power-up the unit in "page 1" to be able to overwrite the default config.

    CDCI6214, Default Configuration
    REFSEL EEPROMSEL Config Selected I2C Available
    VDDREF/2 VDDREF/2 Fall-Back yes
    VDDREF or GND GND Page 0 no
    VDDREF or GND VDDREF Page 1 yes

    Recommended Sequence, EEPROM Programming in Fall-Back Mode

    1. VDDREF supply still off, RESETN=GND, REFSEL= open, EEPROMSEL = open (tri-state microcontroller pins)
    2. Enable supply VDDREF settles within operation range (1.8V or 2.5V or 3.3 +/-5%) while RESETN = GND
    3. Disenagage reset and release to high logic level, RESETN = VDDREF with REFSEL and EEPROMSEL not actively driven (will default to VDDREF/2 using internal voltage dividers)
    4. Start I2C communication using slave address 0x74. Device ACKs transfers.
    5. Functional cross-checks can be done in fall-back mode to confirm that a new PLL configuration is valid and expected outputs are generated. Write custom configuration to device and manually calibrate VCO to see PLL outputs by sending recal=1.
    6. EEPROM can be overwritten using "register commit" or "eeprom direct access" flow described in the data sheet (section 8.5.2 in Rev A).
    7. Power cycle of VDDREF and applying a valid REFSEL and EEPROMSEL logic level will load the new custom config from the EEPROM.

    Recommended Sequence, EEPROM Programming in Normal Operation from Page 1

    1. VDDREF supply still off, RESETN=GND, prepare to drive REFSEL= VDDREF or GND, EEPROMSEL = VDDREF
    2. Enable supply VDDREF settles within operation range (1.8V or 2.5V or 3.3 +/-5%) while RESETN = GND
    3. Disenagage reset and release to high logic level, RESETN = VDDREF with REFSEL at a valid logic low or high level and EEPROMSEL at logic high level.
      1. Should the provided reference frequency be 25 MHz, or close to 25 MHz, the outputs may start driving 100 MHz clocks.
    4. Start I2C communication using slave address 0x76. Device ACKs transfers.
    5. EEPROM can be overwritten using "register commit" or "eeprom direct access" flow described in the data sheet (section 8.5.2 in Rev A).
    6. Power cycle of VDDREF and applying a valid REFSEL and EEPROMSEL logic level will load the new custom config from the EEPROM.

    Best regards,

    Patrick

  • 0 in reply to Patrick Kammermayer
    Prodigy 30 points

    Thank you very much for your reply

  • 0 in reply to Patrick Kammermayer
    Prodigy 30 points

    hi  Patrick

    Recommended Sequence, EEPROM Programming in Fall-Back Mode

    1. VDDREF supply still off, RESETN=GND, REFSEL= open, EEPROMSEL = open (tri-state microcontroller pins)
    2. Enable supply VDDREF settles within operation range (1.8V or 2.5V or 3.3 +/-5%) while RESETN = GND
    3. Disenagage reset and release to high logic level, RESETN = VDDREF with REFSEL and EEPROMSEL not actively driven (will default to VDDREF/2 using internal voltage dividers)
    4. Start I2C communication using slave address 0x74. Device ACKs transfers.
    5. Functional cross-checks can be done in fall-back mode to confirm that a new PLL configuration is valid and expected outputs are generated. Write custom configuration to device and manually calibrate VCO to see PLL outputs by sending recal=1.

    wen I  finish 5 steps  the pll is locked   but no clock output   

    and then i manually create the SYNC pulse but no clock output   also？？？

  • 0 in reply to li wang
    TI__Expert 5325 points
    Hello Li,
    can you please provide more details about your application setup?
    What is your input reference and how did you terminate the outputs?
    When you take the fall-back mode default, the outputs need to see 100 Ohm differential termination. You can also AC-couple and then use 50 Ohm of a scope to see the clocks toggling.
    Did you try switching the output type to LVCMOS to avoid dependencies on the output termination?

    Best regards,
    Patrick