Hi,
I use latest version of TICS Pro (1.6.8.0 / build date 08-Jun-18 / part version 2017-01-30) to assist in finding the configuration settings of the LMK04610.
While changing the CLK0/1 PLL1_RDIV settings I found unexpected behavior.
Any PLL1_RDIV setting below 10 gives the expected result. However any value 10 or higher gives (I think) the wrong result. As a test I checked all effective divider values for setting 1 through 25:
selected PLL1_RDIV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
effective RDIV 1 2 3 4 5 6 7 8 9 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
So, for example, CLK_in = 100MHZ, PLL1_RDIV=20, expected CLK = 5MHz, TICS PRO tool CLK = 3.125MHz (=1/32).
My question: is this a bug in TICS PRO, a bug in LMK04610, or some undocumented feature of LMK04610?
Regards,
Paul
