Allowable jitter on CDCE706 sample clock?

Roddy Vann

Other Parts Discussed in Thread: CDCE706, CDCE72010, CDC7005, CDCE62002

I am using a CDCE706 to frequency-multiply and jitter-clean a reference clock of 10 MHz up to 250 MHz. What is the allowable jitter on the input clock in order to achieve the output jitter values in the CDCE706 datasheet?

over 14 years ago

0 mapefer3 over 14 years ago

TI__Expert 5725 points

The jitter figures (peak to peak and cycle to cycle) on the datasheet relate to a specific device configuration. For different setups, different performances are expected.

CDCE706 is a general purpose clock generator that would not be suitable to clean the jitter of the input clock. To achieve that, I would suggest taking a look at CDC7005, CDCE72010. They will provide the best jitter cleaner performance but it requires an external VCXO.

CDCE62002 will clean also the jitter of your input without the need of an external VCXO but the rms jitter of the output would be worse than the above mentioned, although still within 1ps rms jitter. For this type of device to meet the datasheet performance the input clock should have less than 2ps rms jitter.

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Allowable jitter on CDCE706 sample clock?