• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 477 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828BEVM: Single PLL Operation of Device and Software Support

Keith clark
Prodigy 130 points
Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK04828

Hi,

I wonder if you can help me please?

I have inherited a project from a colleague who has now left and am trying to see if the design is reasonable. Essentially he used a LMK04828BISQ (Clock Jitter Cleaner with Dual Loop PLLs) to produce a series of 100 MHz and 200 MHz clocks from a 10 MHz LVDS TCXO. However, he only used half the chip and fed the TCXO into pins 43 / 44 (OSC in) thus bypassing the first PLL. I have 3 questions:-

1). When using a TCXO rather than degraded clocks that have travelled some distance is it reasonable to use the chip in this manner or will it degrade the jitter performance?

2). Would it make more sense and produce less jitter if the TCXO was say 50 or 100 MHz?

3). I have tried to use the TI Clock Design Tool version 1.3.5 to check the loop filter design. However it doesn’t appear to support the mode I am forced to use as it immediately starts to use both PLL sections. Is there a work around for this please? Also in the select solution part of the program there are 2 options for the LMK04828B VCO0 and VCO1, what is the difference between them?

Many thanks for your help

Best regards

Keith

  • 0
    TI__Guru** 106720 points
    Hi Keith,

    Your colleague was using the PLL2 to generate clean clocks, he was not intended to use it as a jitter cleaner. This configuration is possible.
    Yes, for clock generation, it is suggested to use a higher frequency reference clock. However, >50MHz TCXO is not common. If temperature compensation is not needed, you can use a 100MHz XO.
    Please use PLLatinum Sim to design the loop filter. You can select "Advanced" Feature Level for more options.
    The tuning range of VCO1 is smaller, so its phase noise is better.
  • 0 in reply to Noel Fung
    Prodigy 130 points

    Hi Noel,

    Many thanks for your prompt reply. I am attempting to do what you suggested using PLLatinum Sim. I have loaded the desired device the LMK04828, assumed a 10 MHz input oscillator (because that is what is currently fitted (we have 100 MHz TCXO's now and may substitute them later but for now I'm trying to duplicate what we have in circuit). I have set a Fpd of 10 MHz, a second order loop filter and a Fvco of 3000 MHz which is in the tuning range. The feedback path to the Fpd is therefore 300 and for a 100 MHz O/P the O/P divider needs to be set to 30 and for a 200 MHz O/P this needs to be set to 15. However, this box turns red and if the mouse is hovered over it then it simply says "VCO output divider does not support this value".

    What values are supported? How do I know what are allowable values for each of the boxes?

    In addition if I press "Calculate Loop Filter " the red colour disappears, does this mean the results are now valid?

    Many thanks for any help you can offer, I hope the attached screen shot shows what I have tried.

    Best regards

    Keith

  • 0 in reply to Keith clark
    TI__Mastermind 33270 points

    Hi Keith,

    I help maintain PLLatinum Sim. Those values are valid divide values, but our support for LMK devices was in beta on the version of PLLatinum Sim in your screenshot, so there were still some simulation rules that needed to be updated. We just released a new version of the software midway through last month, which improved support for LMK devices significantly. I recommend reinstalling PLLatinum Sim by getting the latest version of the software from http://www.ti.com/tool/PLLATINUMSIM-SW.

    The LMK04828 contains integrated programmable 3rd and 4th order loop filter components, so for your filter architecture design you will want to select 4th order for your filter order. The "Forced Components" grouping includes a list of possible options for C3, C4, R3, and R4.

    For devices with integrated loop filters, I find the optimizer under the "Performance Summary" grouping is very helpful. You can select a parameter to optimize such as jitter or analog lock time, optionally set the preference order and maximum acceptable value for multiple other optimized parameters (if unsure, disable or set the max values to something very large), and adjust the total time spent searching through filter parameters and forced components. Then, clicking on "Calculate Loop Filter" will automatically search through the filter components C1-C4 and R2-R4, as well as the range of any parameter with the "Auto" box selected. For short sweeps this should take less than a minute, but if the filter parameter or forced component time is increased, or if the "Auto" box is selected on many filter parameters and the range to search is very wide, you may want to increase the "Max. Calculation Time" in the upper left panel to support the longer calculation time required.

    As I was looking through the optimizer, I noticed that there is still a mistake in the rules which handle R3-R4 forced values for LMK04828, so I have updated them and included them in this post. To use the updated rules, go to C:\Program Files (x86)\Texas Instruments\PLLatinumSim (or wherever the install directory is located) and copy the new PLLatinumSimDevices.dat file into the directory.

    PLLatinumSimDevices.dat

    Also, take a look at the "?" boxes next to the group dialog options for more information on how to use the simulator effectively.

    Regards,