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LMK04826: LMK04826 Locking Issue

Part Number: LMK04826

Dear. Hao Z

The previous enquiry is at the link below.
After 50 ohms was removed, I thought the result was OK.
However, problems occur during the tests with the higher equipment.

https://e2e.ti.com/support/clock-and-timing/f/48/p/800136/2972151

Enter the Clock through the RF cable from the higher equipment.

The clock entered is as follows.(10Mhz result)

The length of the RF cable is 50cm.
10Mhz Level is 7dBm.
I think Rising time and Vpp are normal.
10Mhz is entered as CLKIN1 on the LMK04826.

What is the cause of LMK's PLL lock failure?

Please review

Thank you.

  • Hello Henry,

    I am helping Hao with this question. Is the oscilloscope image above the clock signal before it is fed into the board? Or is it the signal seen by the LMK04826 at the CLKin1 pin? It may be that the signal seen at the CLKin1 pin does not look like the signal being fed into the oscilloscope.

    Can you measure the slew rate of the signal? I can't tell from the resolution of the image. It is probably sufficient, but good to check.

    Regards,

  • Hello Derek Payne.

    The input of CLKIN1 was measured.

    It is not possible to measure slew.

    If the length of the RF cable is changed to 20cm, it cannot be locked.

    What other causes may occur?

    Thank you

  • Henry,

    CLKin_SEL1 may be used to confirm that CLKin1 is selected internally, and the device is not locking to noise from a different clock input. Can you check this? If you are sure that CLKin1 is being used, can you set CLKin_SEL1 to indicate CLKin1 LOS? This may indicate a different issue, such as improper soldering or IC damage.

    Regards,

  • Henry,

    I haven't heard back from you in a while. I will assume you resolved the issue on your own. But if you still need assistance, please reply to this thread with an update.

    Regards,