LMK04832: Clock connections

art arty

Prodigy 140 points

Part Number: LMK04832

What do these connections mean? Are they optional? Is there a mistake?

over 6 years ago

0 Derek Payne over 6 years ago

TI__Mastermind 34330 points

The diagram is not totally clear, but these lines should only refer to the divider bypass option available on even clock outputs. This is described in section 8.1.9.2 of the datasheet for the LMK04832:

Even clock outputs (CLKoutX) of the LMK04832 may bypass the clock divider to achieve the best possible noise floor and output swing. In this mode, the only usable output format is CML.

I will make a note to update Figure 6 in our next datasheet revision pass. Thanks for bringing this to our attention.

Regards,

0 art arty over 6 years ago in reply to Derek Payne

Prodigy 140 points

Thanks for your answer. Will something like that be correct?

0 Derek Payne over 6 years ago in reply to art arty

TI__Mastermind 34330 points

Please take a look at Figure 7, which explains the bypass path. Bypass travels through a polarity mux and a bypass mux, and feeds directly into the CML output buffer. When the bypass path is not used, the CML buffer is fed logic low.

Regards,

Clock & timing

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LMK04832: Clock connections