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LMK04828: How to prevent device clock breakup at 9.3.2.1.1?

Kazuhiko Hirano
Genius 15268 points
Part Number: LMK04828

Hello,

 

My customer has questions about 9.3.2.1.1 Setup of SYSREF Example in the datasheet.

 

On step#2, since the Fixed digital delay is used, device clocks are breakup at the SYNC.

To prevent this breakup, Dynamic digital delay should be used instead at the step#2?

Or device clock output should be disabled till the step#2 and enabled before the step#3?

 

Best regards,

 

K.Hirano

  • 0
    TI__Mastermind 33800 points

    Hello Hirano-san,

    Dynamic digital delay could be used at step #2 to prevent clock breakup. However, the user would need to know the phase offset of each device clock and the SYSREF. Often, users must SYNC the clocks because they have no way of measuring the phase offset of each device clock or the SYSREF.

    The output format could be set to powerdown during step #2, and after the SYNC events are complete the output format could be set to the desired value. Setting output format to powerdown avoids clock breakup, but it could create runt pulses when the output format is changed.

    There are two other options for avoiding clock breakup with SYNC:

    1. Initialize the device with the SYNC pin asserted. SYNC_MODE mux initializes to SYNC Pin state, SYSREF_MUX initializes to Normal SYNC state, and all SYNC_DISx bits initialize deasserted (allows reset). On startup, the output dividers will be held in the reset state, and the output clocks will only begin after the SYNC pin is deasserted.
    2. Enable SYNC_PLL1_DLD or SYNC_PLL2_DLD. This option asserts a SYNC signal on startup (like the first option), as long as the corresponding PLL is unlocked. When the corresponding PLL locks, the SYNC signal will be deasserted and the dividers will begin counting. Note that this option only works if the corresponding PLL is used, and will not work in distribution mode.

    Regards,