On my design, there are four TLK3101transceivers and two CDCM61002, one of CDCM61002 is for generating four 150MHZ LVCMOS clock sources to drive four TLK3101 transmit sides and the other CDCM61002 is for generating two LVDS clock sources to drive two Virtex 5 FPGAs. On the receiver side of TLK3101, there are four 150MHZ output clocks (RCLK) coming out of TLK3101, which are going send to Virtex 5s to capture input data from TLK3101. My question is: 1. Which jitter cleaner from TI could be connected between 150MHZ RCLK of TLK3101 and Virtex 5 to reduce jitter? 2. Should jitter cleaner is needed between the output clock of CDCM61002 and input clock of TLK3101to reduce jitter further? 3. Is there any recommended input oscillator settings for CDCM61002, on SCAA111 application notes, there didn’t show any recommended input oscillator settings.
How about using CDCV304 to implement jitter cleaner function?
Many thanks in advance.
