Hello Team,
I got some questions from customer about the CDCE913-Q1.
Q. How much propagation delay from VDD(1.8V) ramp up to start output clock?
Q. How much propagation delay from VDD(1.8V) ramp down to stop output clock?
[Condition]
VDD = 0V~1.8V, VDDOUT=3.3V, PLL is used.(NOT bypassed)
Input clock = 27MHz, Output clock =27MHz, 74.1774MHz
Thanks,
Yuta Kurimoto