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LMH1981: Circuit design verification

Balkis Mahammad
Prodigy 130 points
Part Number: LMH1981

Dear team

I am using LMH1981 IC in my application of sync separator design. Here I am taking HSOUT and  VSOUT fed to the FPGA.

But in page 18 of datasheet it says that "All output signals should have a resistive load of about 10 kΩ and capacitive load of less than 10 pF, including parasitic capacitances for optimal signal quality."

but in the reference design i was able to find these load circuit.

Kindly let me know whether these load termination is required and why?

i have attached the my design circuit for your reference, let me know if there need of deviation in the design

Thanks and Regards

Balkis

  • 0
    TI__Expert 8065 points

    Hello Balkis,

    We do not have the reason for the statement on page 18 although from the datasheet statement it seems related to best timing jitter performance. This is optional as our offered EVM's do not offer these settings.

    The only difference I see from out test circuit found in Figure 2 is a tie from 'CVBS/Y/G', or 'TRI_LEVEL_INPUT' on your schematic, to ground. Please make sure you are impedance matching this as a 75 ohm coaxial connection is expected here or trace to another device and I'm unable to see where 'TRI_LEVEL_INPUT' is terminated.

    The unused output pins 9 (Video Format), 12 (Composite Sync), 13 (Burst/Back Porch Timing), and 14 (Odd/Even Field) can be left as such but if you want to monitor Composite Sync as well you can follow similar termination rules as the VSOUT and HSOUT.

    Hopefully this was helpful!