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LMX2820: setting up MASH DELAY

Obinna Ezeilo
Intellectual 2385 points
Part Number: LMX2820
Other Parts Discussed in Thread: LMX2572

Hi team, 

My customer is evaluating the LMX2820 EVM and had the following challenge: 

  1. I set the LMX2820 frequency 2200 MHz at OUTA (using LMX2820 Eval)
  2. PLL_N=44 PLL_NUM=0 PLL_DEN=200 VCO FREQ 8800 MHz
  3. MASH ORDER = 3. (No problem to this point) 
  4. MASH_SEED_ORDER =10
  5. ENABLE/DISABLE FCAL in Reg0
  6. ENABLE/DISABLE Phase Sync Bit 15 Reg 1
  7. LOAD REG 40 and REG 41 with MASH_SEED_ORDER number 10 or 40 or 100

I don’t see any phase shift change at the OUTB output. What I see are some phase jumps when I reload Reg 0.

This is the only thing that seems to effect the OUTB phase. 

What am I doing wrong?

Do you have any working example of the register loading to implement the phase shift using MASH?

 

We were able to get LMX2572 to work with MASH phase shift, but there seems to be some difference between the two.

Of course we realize they have different register definitions, but we tried to move the concept from one to another and this did not work

 Can you please help here. 

Thanks for the support and looking forward to your response.

Obinna. 

  • 0
    TI__Mastermind 33430 points

    Hi Obinna,

    Have you ensured that MASHSEED_EN=1 when performing the phase adjustments?

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    TI__Intellectual 2385 points

    Hi Derek, 

    MASH ENABLE is enabled. Customer would like to know what triggers the phase change.

    The manual for LMX2820  refers to MASH_RST_N bit which they can’t find it in the list registers. 

    Can you advise how to set it?

     

    Could you also provide of what has to be set in order to get the phase shift incremented?

    Can you set up LMX2820 to MASH shift phase and send me the register dump. Customer suspect that one of the registers

    Is not set up properly.

     

    To be clear what would work for customer would be

    1. Reg. dump for MASH phase shift enabled  and operating
    2. Short list if registers (bits) that have to be updated in order to shift phase

     

    They would preload the reg. content then load registers to keep moving phase. 

    Thanks for the support. 

    Kind regards, 

    Obinna. 

  • +1 in reply to Obinna Ezeilo
    TI__Guru** 107030 points

    Hi Obinna,

    Were you talking about the phase adjustment function as outlined in datasheet section 7.3.12.2?

    This function works only in final silicon, if your silicon has PLMX marking, it is a prototype silicon and it does not support this function.