question about LMK04808 dual pll, int VCO, 0-delay

I think because the GCD(122.88, 81.92) = 40.96 and 122.88/40.96 = 3, which is why you have the -120, 0, +120 phases.  I think you're having this issue in two places.  1st in the reference you provide, 2nd in the feedback for 0-delay.

First)

As for your case, you say you are sending a 122.88 MHz clock that is synched with 81.92 MHz.  There is no telling which edge of the 122.88 MHz the 0-delay feedback will lock to with respect to the 81.92 MHz clock.  The 81.92 is synched with only 1 of 3 edges of 122.88 MHz.

Second)

When doing 0-delay, feeding the lowest frequency back is really not the key.  Finding the GCD of the input with all frequencies for which you care to have deterministic (0-delay) tells you the low frequency you really need to feedback to ensure 0-delay.  In this case it's 40.96 MHz.

So the upshot of all this, the 0-delay feature is preserving you to the three phases vs. the 36 possible phases (assuming 2949.12 MHz VCO frequency) you could be experiencing at 81.92 MHz.

So I think you got 0-delay configured correctly, but be aware of the 0-delay configuration information for CodeLoader in the eval board instructions.

73,
Timothy

Ramakrishna Bachimanchi said:

thanks for the explanation and I understand this as I was using cdcm7005 with 70 MHz reference and 112 MHz crystal and we ran into the same issue. I was hoping LMK048xx would simplify this, apparently not.

0-delay provides a way to feed-back output clocks to include their output divides in the PLL N loop. By doing this a phase comparison is made between input and output which results in a fixed, or “0-delay,” between the input clock and the output clock.

Ramakrishna Bachimanchi said:

I am still confused with the statement in the data sheet that says
"The 0-delay mode synchronizes the input clock phase to the output clock phase.
Without using 0-delay mode there will be D possible fixed phase relationships from clock input to clock output
depending on the clock output divide value".
Now what you are explaining is the relation between vco and the output clock. Datasheet doesn't say anything about having possible fixed relationships between vco and the output clock

You will always have a fixed phase relationship between the output clock and the VCO clock because there is always a VCO clock edge associated with every edge of the ouput. The D possible fixed phase relationships from clock input to clock output relates to the clock divider introducing phase uncertainty from the lower frequency which is the input reference. Higher input frequencies may reduce the “D possible fixed phase relationships”. For example:

• 50 MHz input using 3000 MHz VCO to 50 MHz output will have 60 possible phase relationships.
• 100 MHz input using 3000 MHz VCO to 50 MHz output will have 30 possible phase relationships.
• 50 MHz input using 3000 MHz VCO to 100 MHz output will have 30 possible phase relationships.
• 100 MHz input using 3000 MHz VCO to 100 MHz output will have 30 possible phase relationships.
• 200 MHz input using 3000 MHz VCO to 100 MHz input will have 15 possible phase relationships.
• 100 MHz input using 3000 MHz VCO to 200 MHz input will have 15 possible phase relationships.
• 200 MHz input using 3000 MHz VCO to 200 MHz input will have 15 possible phase relationships.

Ramakrishna Bachimanchi said:

Moreover I didn't see any difference with the eval board whether I used 0-delay mode or not with the set up I described
I am not sure what this 0-delay loop is doing. The description, operation and your explanation is not very clear to me
I simply don't see the difference between 0-delay loop and without 0-delay loop

I do apologize that the GUI isn’t setup better for implementing 0-delay, meaning when you include the clock output divide, you must reduce the PLLX N divider to which the 0-delay feedback occurs by the CLKoutX divide value. This can result in output frequencies being reported incorrectly. What is key is the divider values programmed, not the frequencies.  Refer to EVM instructions for assistance on this.

Ramakrishna Bachimanchi said:

another comment on the 0-delay described in LMK0482xB
it specifically says "Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux" which means as long as I don' change anything physically the phase relationship between PLL input clock and output clock should stay the same (turn it on/off or reprogram the chip etc.)

Correct, however the frequency of the clock you feedback is critical to achieve this functionality.

Ramakrishna Bachimanchi said:

I am not sure, if this is not the case what 0-delay is
and it says the same thing again
"Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value"
my understanding from this statement is I don't have to worry about different lock points. I have asked couple of engineers at my work place what they understand from this statement and they all said, they have some algorithm inside the chip that makes sure it locks to the same point for two different frequencies (instead of multiple lock points as long nothing changes physically ..adding cable, attenuators etc.) . I would really appreciate a clear explanation on the 0-delay as I am planning to use the chip in a design where single lock point between the input frequency and output frequency are critical

The 0-delay feature works by feedback of the output clock to the phase detector for comparison. So in the cascaded dual loop, there are two phase detectors. The first phase compare is with PLL1 and the second with PLL2.

• For PLL1, between CLKinX to OSCin there is always “0-delay” or “fixed-delay” because there is no output divide feeding PLL2 input which is not in the PLL1 loop.
  • Note you could use PLL1_R_DLY and PLL1_N_DLY to adjust phase.
  • Note if you used the OSC Divider to an OSCoutX output, you can include this divide in the feedback path to PLL1 N to ensure 0-delay for OSCoutX by choosing OSCout0_MUX = OSC Divider. However for clocks from PLL2 using OSCin for PLL2 R, this is not required because PLL1’s feedback loop isn’t missing any ‘output dividers’ feeding PLL2 R.
  • For PLL2 in 0-delay mode, between OSCin and CLKoutX there is fixed “0-delay” or “fixed-delay” where CLKoutX is the clock used for 0-delay feedback.
    • This is achieved by looping back the CLKoutX to the PLL2 N divider for inclusion in the loop which compares the phase with the input clock.
    • Other clocks can share this “0-delay” or “fixed-delay” attribute when all the clocks are SYNCed together. But be aware these other clocks may or may not match OSCin phase depending on their integer relationship to the CLKoutX fed back to phase detector and the OSCin frequency.
    • One other detail is that if the PLL2 doubler is engaged, this will introduce a possible phase shift from input to output equal to doubled frequency. Using nested 0-delay eliminates this variation because this doubler is now “in the loop” where the CLKinX signal is compared directly to a CLKoutX signal. Because nested 0-delay has only one phase detector, it may also reduce phase variation from input (CLKinX) to output (CLKoutX).