ADS54J60EVM: Clocking & constraining on ZCU102

Anastasios,

1. This info should be in the documentation that was provide.

2. The LMK is only rated for 1GHz so I would suggest using the LMK_Config_Onboard_983.04MSPS.cfg. You can use whatever ADS54J60 file you want. 

3. SYSREF = data rate out of ADC / (K * N) where N is any whole integer. If you have the ADC sampling at 983.04Msps and you are using 4x decimation, the data rate out of the ADC = 245.76Msps.

4. For the ZCU102, use pins G9 and G10 as these signals come from the LMK on the EVM. The ADC has SYSREF coming from the LMK as the EVM default mode.

Regards,

Jim  

Jim,

Thank you for clarifying my issues. Reading again the TI-204C IP reference documentation revealed that the lowest number of bytes ber lane is 4. This means that I will use only the lower 16-bits (out of 32) of each lane.

I have one more question as I still cannot establish communication between ADS54J60EVM and the JESD204B RX side on the FPGA.

I have set the following constraints:

FMC C6/C7 & A14/A15 for mgt_lane_rx(p/n)
FMC D4 & D5 for refclk (constrained at 250Mhz)
FMC G9 & G10 for sysref (not constrained at any specific freq.)
FMC H31 for sync_n (I had initially used G12/G13 diff. FMC pins for sync but I changed it)
FMC G2/G3 for sys_clk (constrained at 250Mhz but it didn't work. No signal came from the ADC to these pins).

The IP documentation says (and I quote):

"If the rx_sys_clock is sourced independently, there are two options:
- If the frequency is exactly at the lower limit as per the table above, it should still be generated from a common root clock being used to generate ADC as well as the MGTREFx clocks. This will ensure that any drift in the clock impacts all the components together."

But I cannot just use the D4 & D5 FMC refclk pins, nor I can somehow split the clock as it is handled internally in the TI IP core. Are there any other pins (that might be missing from the ADS54J60EVM schematic) capable of driving the sys_clk coming out of the ADC module?

PS. Any guide on how to properly set the SYSREF divider on the ADS54Jxx GUI will be greatly appreciated. It needs to be: "data rate out of ADC / 128".

Kind regards,
Anastasios

Anastasios,

If you plan on using H31 for SYNC, you must move the shunt on SJP3 from pins 2-3 to 1-2. By default, the ADC54J60EVM uses pins G12/G13 for SYNC. There are no signals connected to G2/G3. If you need a core clock for the FPGA you must use FMC pins G6/G7. This provides a second clock from the LMK.ADS54J42_Fs_552.96MHz_LMFS_2242.pptx

To set the SYSREF divider, go to the SYSREF and SYNC tab in the GUI and use the SYSREF Divider box to enter your setting. See slide 5 of attached example document.

Regards,

Jim

Jim,

I managed to achieve qpll0 transceiver lock (on both banks). However, even though the TI IP RX instance asserts SYNC~ (drives it to low) it fails to capture any data whatsoever. Both rx_lane_data buses are stuck at 0 and the rx_lane_data_valid signal is again stuck at 0.

I manually selected (from within GUI) the continuous test mode K28.5. Shouldn't I expect to receive constant 0xBC at all lanes? Why am I getting nothing?

I use FMC pins A14/A15 for channel A and FMC pins C6/C7 for channel B. As for the SYNC~ signal I stick to using G12/G13 after using an OBUFDS (without inverting the SYNC~ signal).

Finally, I kindly ask you to provide me any reference design that already incorporates this ADS54J60EVM ADC (or even any TI JESD204 ADC) onto ANY Xilinx target FPGA. I think that I can solve all my issues by having a good reference point as I am new to the TI ecosystem.

PS. There is a reference design for ZCU102 and one of your ADCs but the txn/box link is dead. If this reference design still exists, it will be extremely helpful.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/673902/adc12dj3200evm-kcu105-reference-design-targeted-for-zcu102-byte-ordering

Kind regards,
Anastasios

Anastasios,

See if this reference design helps. It uses an ADS54J20 which is the same as the ADS54J60 only a slower speed grade.

Regards,

Jim

ZCU102_ADS54J20_8224.zip

Jim,

I've got to say a big, big thank you! The reference design proved to be very helpful!

I actually managed to modify it to work for my ADS54J60 ADC. I used the provided configuration (LMFS = 8224 and sys_clock = 122.88Mhz).

RPAT testmode worked perfectly. However, when I hooked up a signal generator in Channel A, the signal I received on the RX core was some form of "0002" (attached ILA screenshot). The signal that I used was a 60Mhz +15dbm sine wave and was provided directly through an SMA cable. I tested higher and lower frequencies but again the only sequence (apart from zeroes) that I got was "0002". Was this a problem with the input signal? What should be the maximum voltage of a given input?

I've got one more question however regarding the LMFS configuration: in the ADS54J60EVM datasheet the FMC pins for each lane/channel are label as DA0P, DA1P, DB0P etc. If I decide to use the LMFS 2441 that uses the ADC lane pins DA1 and DB1 how should I map it to the transceiver lanes? How should I identify the transceiver number? I only know that each quad/bank has 4 lanes and no additional information regarding the indexing.

// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// For example a value of {3,1,0,2} will mean the 
// following:
//   1> Lane 0 of ADC is mapped to Lane 2 of the transceiver
//   2> Lane 1 of ADC is mapped to Lane 0 of the transceiver
//   3> Lane 2 of ADC is mapped to Lane 1 of the transceiver
//   4> Lane 3 of ADC is mapped to Lane 3 of the transceiver

Regards,
Anastasios

Anastasios,

You need to edit both the transceiver and IP components. 

The transceiver needs to first be modified to a two lane transceiver.  After that, the rest of the related parameters need to be edited based on the two lane configuration. 

DA1 will be transceiver 0 and DB1 will be transceiver 1.

Regards,

Jim