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DAC38RF82EVM: board setup with KCU105

Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, LMK04828

Hi,

I am starting to work with DAC38RF82EVM connected to KCU105 through FMC connector.

I am following  'slau711 - March 2017' document to have a working starting point.

I have followed sections 4, 6 & 7.6.2 (PLL mode of DAC38RF82EVM).

Everything seems ok, and I can do all configurations stated in such sections, but finally I am not getting the 1.9592 GHz signal.

The tool versions are:

 - HSDC Pro: v5.2

 - DAC38RF8x: v3p1 / build date: 04 February 2020

 - Vivado: I have tried both 2016.3 and 2021.2

I have already checked the jumper settings of DAC38RF82EVM:

JP1: shunt 2-3

JP2: shunt 1-2

JP3/JP8/JP9/JP10/J11/J22: open

J23: shunt 1-2, 3-4, 5-6 7-8

What checks should I do to narrow the problem?

Thanks,

  Miguel

  • Miguel,

    Shunt JP10 should be shorted. See section 7.6.1 step 2. 

    Regards,

    Jim

  • Jim,

    Thanks for your answer.

    I am following section 7.6.2 (PLL mode) as section 7.6.1 requires a 6 GHz signal generator, and I don't have such generator in hand.

    That´s why I have JP10 left open. However, if you can provide a proven setup for external clock mode not requiring such high frequency (less than 4 GHz would be fine), I will try it.

    Thanks,

      Miguel

  • Miguel,

    Use a 4GHz clock and enter 4000 in the quick start menu in place of the 6000 and re-use all existing values. In HSDC pro GUI, the data rate you will enter will now be 250MHz.

    Regards,

    Jim 

  • Jim,

    I have finally used a 2 GHz clock, as my signal generator doesn´t reach 14 dBm @ 4GHz.  So, I have a clock 14 dBm @ 2 GHz.  I have entered 2000 in the Quick Start tab in place of 6000 and re-used all other values, as you said. In HSDC pro GUI, I have entered 125M as the sample rate. Unfortunately, I am still not seeing any output at J6.  I have checked that JP10 is shunt.

    What checks could I do at this point?

    Regards, 

      Miguel

  • Hi again, Jim,

    On the other hand, I am also trying to get some signal out of DAC EVM following "KCU105 DAC38RF82 JESD REFERENCE DESIGN USER GUIDE".  So, I have generated a bitstream with Vivado 2020.1 for the project KCU105_7p68G_RefDesign.  I am still getting no output.  In this case, after configuring the DAC and programming the KCU105:

     - I press sw5.  After that, LED0 is ON and LED4 is blinking.  

     - Then, I press "Reset DAC JESD Core & SYSREF TRIGGER".  After that, both LED0 and LED4 are off, and I get no output signal.

    Well, any ideas regarding any of the two setups (slau711 or "KCU105 DAC38RF82 JESD REFERENCE DESIGN USER GUIDE") are welcome.

    Regards,

      Miguel

  • Miguel,

    Go back to PLL mode by following the steps in section 7.6.2. After clicking on the "PLL AUTO TUNE" button, follow the steps in the attached slide. If you can get a 100MHz tone out, this will verify the DAC clocking has been setup properly. If this test passes, go back to the DACA tab and set the parameters per the User's Guide as shown in Figure 31. After pressing the "Reset DAC JESD Core & SYSREF TRIGGER", report the status of the LED's on the KCU105.

    If the DAC did not pass the NCO only test, you may be having an issue with your input clock source.

    Regards,

    JimDAC38RF82_NCO_Only_Test_100MHz.pptx  

  • Jim,

    Thanks a lot for your reply.

    I do get the 100 MHz signal. This is the first signal coming out of the EVM...thanks again.

    After pressing "Reset DAC JESD Core & SYSREF TRIGGER", this is the status of the LEDs:

    - LED0, LED1, LED2: off

    - LED3: blinking

    - LED4: blinking faster than LED3

    - LED5: off

    - LED6: blinking (it seems to be the same rate as LED4)

    - LED7: on

    Regards,

      Miguel

  • Miguel,

    Everything appears correct. What is the status of SYNC? Are you getting any DAC alarms or errors now?

    Jim

  • DAC38RF8x EVM screenshots.pptx

    Jim,

    If you refer to the LED labelled 'JESD SYNC' on EVM, it is off.  All these LEDs are off: PLL2 LOCK / STAT0 / STAT1 / LMK LOCK / SPARE 1 / SPARE 2 / JESD SYNC.

    In the Alarm Monitoring tab, I have pressed 'Read Errors' and I am getting no errors.

    Regarding the LEDs on KCU105: after completing all steps of section 7.6.2 (slau711), all LEDs remain in the state I reported before, expept for LED7, which is off.

    I have attached screenshots of the DAC EVM configuration tool. Please, check it.

    Regards, 

      Miguel

  • Miguel,

    Monitor SYNC with Vivado. The SYNC LED tells us nothing. Did you click on "UPDATE NCO" in both Dig tabs? 

    Regards,

    Jim

  • Jim,

    I am programming the bitstream that comes with HSDC Pro v5.20 (KCU105_TI_DHCP.bit), so I don't have any Debug Probe File to monitor SYNC.

    If you can provide a way to do it, that would be great.

    In the previos screenshots, I clicked on 'update NCO' just for DAC A, as it was the only one I am intending to use.

    Regards,

      Miguel

  • Hi Jim,

    I am finally generating the test signal.  I have noticed that in tab LMK04828 --> Clock Outputs, the box 'SDCLKout_PD' for CLKout 0 and 1, was checked.  So, I am now unchecking it every time I press 'Reset DAC JESD Core & SYSREF TRIGGER', and the test signal is generated.

    My point now is that I am not seeing a 1.9592 GHz tone. Instead, I am seeing 1.96025 GHz.  I am reviewing this point.

    Maybe, there is still some missconfiguration, appart from unchecking 'SDCLKout_PD' for CLKout 0 and 1.  Any ideas will be welcome.

    Regards,

      Miguel

  • Miguel,

    The output should be the test frequency input plus the NCO setting. What is the frequency of the input tone, the NCO, and the DAC CLK? If using the DAC PLL, what is the frequency of the reference clock? Could the ref clock be off enough to cause what you are seeing?

    The GUI will set SDCLKout_PD to 1 when you press the RESET DAC JESD to turn off SYSREF, which is not needed once the link is established. I do not think this is causing the frequency difference you are seeing.

    Regards,

    Jim  

  • HI Jim,

    The problem with the frequency difference is solved, it was due to my setup.

    Now, I can generate the test signal as per 'slau711 - March 2017' document.  With the only difference that I have to uncheck SDCLKout_PD for CLKout 0 and 1, every time I press 'Reset DAC JESD Core & SYSREF TRIGGER'.

    Thanks for your support.

    Regards,

      Miguel